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? 2005 microchip technology inc. ds39612b PIC18F6525/6621/8525/8621 data sheet 64/80-pin high-performance, 64-kbyte enhanced flash microcontrollers with a/d
ds39612b-page ii ? 2005 microchip technology inc. information contained in this publication regarding device applications and the like is provi ded only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2005 microchip technology inc. ds39612b-page 1 PIC18F6525/6621/8525/8621 high performance risc cpu: linear program memory addressing to 64 kbytes linear data memory addressing to 4 kbytes 1 kbyte of data eeprom up to 10 mips operation: - dc ? 40 mhz osc./clock input - 4 mhz ? 10 mhz osc./clock input with pll active 16-bit wide instructions, 8-bit wide data path priority levels for interrupts 31-level, software accessible hardware stack 8 x 8 single-cycle hardware multiplier peripheral features: high current sink/source 25 ma/25 ma four external interrupt pins timer0 module: 8-bit/16-bit timer/counter timer1 module: 16-bit timer/counter timer2 module: 8-bit timer/counter timer3 module: 16-bit timer/counter timer4 module: 8-bit timer/counter secondary oscillator clock option ? timer1/timer3 two capture/compare/pwm (ccp) modules: - capture is 16-bit, max. resolution 6.25 ns (t cy /16) - compare is 16-bit, max. resolution 100 ns (t cy ) - pwm output: 1 to 10-bit pwm resolution three enhanced capture/compare/pwm (eccp) modules: - same capture/compare features as ccp - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown on external event - auto-restart master synchronous serial port (mssp) module with two modes of operation: - 2/3/4-wire spi? (supports all 4 spi modes) -i 2 c? master and slave mode two enhanced usart modules: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud rate detect parallel slave port (psp) module external memory interface (pic18f8525/8621 devices only): address capability of up to 2 mbytes 16-bit interface analog features: 10-bit, up to 16-channel analog-to-digital converter (a/d): - auto-acquisition - conversion available during sleep programmable 16-level low-voltage detection (lvd) module: - supports interrupt on low-voltage detection programmable brown-out reset (bor) dual analog comparators: - programmable input/output configuration special microcontroller features: 100,000 erase/write cycle enhanced flash program memory typical 1,000,000 erase/write cycle data eeprom memory typical 1 second programming time flash/data eeprom retention: > 100 years self-reprogrammable under software control power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power-saving sleep mode selectable oscillator options including: - 4x phase lock loop (pll) ? of primary oscillator - secondary oscillator (32 khz) clock input in-circuit serial programming? (icsp?) via two pins mplab ? in-circuit debug (icd 2) via two pins cmos technology: low power, high-speed flash technology fully static design wide operating voltage range (2.0v to 5.5v) industrial and extended temperature ranges device program memory data memory i/o 10-bit a/d (ch) ccp/ eccp pwm mssp/spi?/ master i 2 c? eusart timers 8-bit/16-bit emi bytes # single-word instructions sram (bytes) eeprom (bytes) PIC18F6525 48k 24576 3840 1024 53 12 2/3 14 y 2 2/3 n pic18f6621 64k 32768 3840 1024 53 12 2/3 14 y 2 2/3 n pic18f8525 48k 24576 3840 1024 70 16 2/3 14 y 2 2/3 y pic18f8621 64k 32768 3840 1024 70 16 2/3 14 y 2 2/3 y 64/80-pin high-perfo rmance, 64-kbyte enhanced flash microcontrollers with a/d
PIC18F6525/6621/8525/8621 ds39612b-page 2 ? 2005 microchip technology inc. pin diagrams PIC18F6525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2/cs /p2b re3/p3c re4/p3b re5/p1c re6/p1b re7/eccp2 (1) /p2a (1) rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 re1/wr /p2c re0/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d mclr /v pp /rg5 (2) rg4/ccp5/p1d v ss v dd rf7/ss rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0/flt0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/lvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 64-pin tqfp note 1: eccp2/p2a are multiplexed with rc1 when ccp2mx is set, or re7 when ccp2mx is not set. 2: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled. pic18f6621
? 2005 microchip technology inc. ds39612b-page 3 PIC18F6525/6621/8525/8621 pin diagrams (cont.?d) pic18f8525 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10/cs /p2b re3/ad11/p3c (2) re4/ad12/p3b (2) re5/ad13/p1c (2) re6/ad14/p1b (2) re7/ad15/eccp2 (1) /p2a (1) rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4 rd5/ad5/psp5 rd6/ad6/psp6 rd7/ad7/psp7 re1/ad9/wr /p2c re0/ad8/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d mclr /v pp /rg5 (3) rg4/ccp5/p1d v ss v dd rf7/ss rb0/int0/flt0 rb1/int1 rb2/int2 rb3/int3/eccp2 (1) /p2a (1) rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/lvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo rj0/ale rj1/oe rh1/a17 rh0/a16 1 2 rh2/a18 rh3/a19 17 18 rh7/an15/p1b (2) rh6/an14/p1c (2) rh5/an13/p3b (2) rh4/an12/p3c (2) rj5/ce rj4/ba0 37 rj7/ub rj6/lb 50 49 rj2/wrl rj3/wrh 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp note 1: eccp2/p2a are multiplexed with rc1 when ccp2mx is se t; with re7 when ccp2mx is cleared and the device is configured in microcontroller mode; or with rb3 when ccp2mx is cleared in all other program memory modes. 2: p1b/p1c/p3b/p3c are multiplexed with re6:re3 when eccpmx is set and with rh7:rh4 when eccpmx is not set. 3: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled. rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 pic18f8621
PIC18F6525/6621/8525/8621 ds39612b-page 4 ? 2005 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 21 3.0 reset ....................................................................................................................... ................................................................... 29 4.0 memory organization ......................................................................................................... ........................................................ 39 5.0 flash program memory........................................................................................................ ...................................................... 61 6.0 external memory interface ................................................................................................... ...................................................... 71 7.0 data eeprom memory .......................................................................................................... ................................................... 79 8.0 8 x 8 hardware multiplier................................................................................................... ......................................................... 85 9.0 interrupts .................................................................................................................. .................................................................. 87 10.0 i/o ports .................................................................................................................. ................................................................. 103 11.0 timer0 module .............................................................................................................. ........................................................... 131 12.0 timer1 module .............................................................................................................. ........................................................... 135 13.0 timer2 module .............................................................................................................. ........................................................... 141 14.0 timer3 module .............................................................................................................. ........................................................... 143 15.0 timer4 module .............................................................................................................. ........................................................... 147 16.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 149 17.0 enhanced capture/compare/pwm (eccp) module................................................................................. ............................... 157 18.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 173 19.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 213 20.0 10-bit analog-to-digital converter (a/d) module ............................................................................ ......................................... 233 21.0 comparator module.......................................................................................................... ........................................................ 243 22.0 comparator voltage reference module ........................................................................................ ........................................... 249 23.0 low-voltage detect ......................................................................................................... ......................................................... 253 24.0 special features of the cpu ................................................................................................ .................................................... 259 25.0 instruction set summary .................................................................................................... ...................................................... 275 26.0 development support........................................................................................................ ....................................................... 317 27.0 electrical characteristics ................................................................................................. ......................................................... 323 28.0 dc and ac characteristics graphs and tables ................................................................................ ...................................... 357 29.0 packaging information...................................................................................................... ........................................................ 373 appendix a: revision history................................................................................................... .......................................................... 377 appendix b: device differences................................................................................................. ........................................................ 377 appendix c: conversion considerations .......................................................................................... ................................................. 378 appendix d: migration from mid-range to enhanced devices....................................................................... .................................. 378 appendix e: migration from high-end to enhanced devices........................................................................ .................................... 379 index .......................................................................................................................... ........................................................................ 381 on-line support................................................................................................................ ................................................................. 391 systems information and upgrade hot line ....................................................................................... ............................................... 391 reader response ................................................................................................................ .............................................................. 392 PIC18F6525/6621/8525/8621 product identification system ........................................................................ .................................... 393
? 2005 microchip technology inc. ds39612b-page 5 PIC18F6525/6621/8525/8621 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, pleas e specify which device, revisi on of silicon and data sheet (inclu de liter- ature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC18F6525/6621/8525/8621 ds39612b-page 6 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 7 PIC18F6525/6621/8525/8621 1.0 device overview this document contains device specific information for the following devices: PIC18F6525 pic18f6621 pic18f8525 pic18f8621 this family offers the advantages of all pic18 microcontrollers ? namely, high computational performance at an economical price ? with the addition of high-endurance enhanced flash program memory. the PIC18F6525/6621/8525/8621 family also provides an enhanced range of program memory options and versatile analog features that make it ideal for complex, high performance applications. 1.1 key features 1.1.1 expanded memory the PIC18F6525/6621/8525/8621 family provides ample room for application code and includes members with 48 kbytes or 64 kbytes of code space. other memory features are: data ram and data eeprom: the PIC18F6525/ 6621/8525/8621 family also provides plenty of room for application data. the devices have 3840 bytes of data ram, as well as 1024 bytes of data eeprom for long term retention of nonvolatile data. memory endurance: the enhanced flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles ? up to 100,000 for program memory and 1,000,000 for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. 1.1.2 external memory interface in the unlikely event that 64 kbytes of program memory is inadequate for an application, the pic18f8525/8621 members of the family also implement an external memory interface. this allows the controller?s internal program counter to address a memory space of up to 2 mbytes, permitting a level of data access that few 8-bit devices can claim. with the addition of new operating modes, the external memory interface offers many new options, including: operating the microcontroller entirely from external memory using combinations of on-chip and external memory, up to the 2-mbyte limit using external flash memory for reprogrammable application code or large data tables using external ram devices for storing large amounts of variable data 1.1.3 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. this is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. 1.1.4 other special features communications: the PIC18F6525/6621/8525/ 8621 family incorporates a range of serial communi- cation peripherals, including 2 independent enhanced usarts and a master ssp module capa- ble of both spi and i 2 c (master and slave) modes of operation. also, for PIC18F6525/6621/8525/8621 devices, one of the general purpose i/o ports can be reconfigured as an 8-bit parallel slave port for direct processor to processor communications. ccp modules: all devices in the family incorporate two capture/compare/pwm (ccp) modules and three enhanced ccp (eccp) modules to maximize flexibility in control applications. up to four different time bases may be used to perform several different operations at once. each of the three eccps offer up to four pwm outputs, allowing for a total of 12 pwms. the eccps also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and half-bridge and full-bridge output modes. analog features: all devices in the family feature 10-bit a/d converters with up to 16 input channels, as well as the ability to perform conversions during sleep mode and auto-acquisition conversions. also included are dual analog comparators with programmable input and output configuration, a programmable low-voltage detect module and a programmable brown-out reset module. self-programmability: these devices can write to their own program memory spaces under internal software control. by using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field.
PIC18F6525/6621/8525/8621 ds39612b-page 8 ? 2005 microchip technology inc. 1.2 details on individual family members the PIC18F6525/6621/8525/8621 devices are avail- able in 64-pin (PIC18F6525/6621) and 80-pin (pic18f8525/8621) packages. they are differentiated from each other in four ways: 1. flash program memory (48 kbytes for PIC18F6525/8525 devices; 64 kbytes for pic18f6621/8621 devices). 2. a/d channels (12 for PIC18F6525/6621 devices; 16 for pic18f8525/8621 devices). 3. i/o ports (7 on PIC18F6525/6621 devices; 9 on pic18f8525/8621 devices). 4. external program memory interface (present only on pic18f8525/8621 devices) all other features for devices in the PIC18F6525/6621/ 8525/8621 family are identical. these are summarized in table 1-1. block diagrams of the PIC18F6525/6621 and pic18f8525/8621 devices are provided in figure 1-1 and figure 1-2, respectively. the pinouts for these device families are listed in table 1-2. table 1-1: PIC18F6525/6621/8525/8621 device features features PIC18F6525 pic18f6621 pic18f8525 pic18f8621 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 48k 64k 48k 64k program memory (instructions) 24576 32768 24576 32768 data memory (bytes) 3840 3840 3840 3840 data eeprom memory (bytes) 1024 1024 1024 1024 external memory interface no no yes yes interrupt sources 17 17 17 17 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h, j timers 5 5 5 5 capture/compare/pwm modules 2 2 2 2 enhanced capture/compare/ pwm module 3333 serial communications mssp, addressable eusart (2) mssp, addressable eusart (2) mssp, addressable eusart (2) mssp, addressable eusart (2) parallel communications psp psp psp psp 10-bit analog-to-digital module 12 input channels 12 input channels 16 input channels 16 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) programmable low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 77 instructions 77 instructions 77 instructions 77 instructions package 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
? 2005 microchip technology inc. ds39612b-page 9 PIC18F6525/6621/8525/8621 figure 1-1: PIC18F6525/6621 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode and control osc1/clki osc2/clko v dd , porta portb portc ra4/t0cki ra5/an4/lvdin rb0/int0/flt0 rc0/t1oso/t13cki rc1/t1osi/eccp2 (1) / p2a (1) rc2/eccp1/p1a rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 brown-out reset ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 timing generation rb1/int1 data latch data ram (3.8 kbytes) address latch address<12> 12 bank 0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply w 8 bitop 8 8 alu<8> 8 test mode select address latch program memory (48/64 kbytes) data latch 20 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch portd rd7/psp7 rb2/int2 rb3/int3 pclatu pcu precision reference band gap porte portg rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg4/ccp5/p1d re6/p1b re7/eccp2 (1) /p2a (1) re5/p1c re4/p3b re3/p3c re2/cs /p2b re0/rd /p2d re1/wr /p2c osc2/clko/ra6 v ss note 1: eccp2/p2a are multiplexed with rc1 when ccp2m x is set, or re7 when ccp2mx is not set. 2: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled. portf rf6/an11 rf7/ss rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf0/an5 rf1/an6/c2out rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd mclr (2) mclr /v pp /rg5 (2) :rd0/psp0 eusart1 comparator mssp eusart2 10-bit adc timer2 timer1 timer3 timer4 timer0 ccp4 ccp5 lvd eccp2 eccp3 eccp1 bor data eeprom
PIC18F6525/6621/8525/8621 ds39612b-page 10 ? 2005 microchip technology inc. figure 1-2: pic18f8525/8621 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode and control osc1/clki osc2/clko brown-out reset eusart1 comparator mssp eusart2 timing generation 10-bit adc data latch data ram (3.8 kbytes) address latch address<12> 12 bank0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply w 8 bitop 8 8 alu<8> 8 te s t m o d e select address latch program memory (48/64 kbytes) data latch 20 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rom latch pclatu pcu precision reference band gap porth rh0/a16:rh3/a19 (4) portj rj6/lb rj7/ub rj5/ce rj4/ba0 rj3/wrh rj2/wrl rj0/ale rj1/oe timer2 timer1 timer3 timer4 timer0 note 1: eccp2/p2a are multiplexed with rc1 when ccp2mx is set; with re7 when ccp2mx is cleared and the device is configured in microcontroller mode; or with rb3 when ccp2mx is cleared in all other program memory modes. 2: p1b/p1c/p3b/p3c are multiplexed with re6:re3 when eccpmx is set and with rh7:rh4 when eccpmx is not set. 3: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled. 4: external memory interface pins are multiplexed with portd (ad7:ad0), porte (ad15:ad8) and porth (a19:a16). ccp4 ccp5 rh7/an15/p1b (2) rh6/an14/p1c (2) rh5/an13/p3b (2) rh4/an12/p3c (2) lvd porta portb portc ra4/t0cki ra5/an4/lvdin rb0/int0/flt0 rc0/t1oso/t13cki rc2/eccp1/p1a rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 rb1/int1 portd rb2/int2 rb3/int3/eccp2 (1) / p2a (1) porte portg rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg4/ccp5/p1d re6/ad14/p1b (2,4) re7/ad15/eccp2 (1) /p2a (1,4) re5/ad13/p1c (2,4) re4/ad12/p3b (2,4) re3/ad11/p3c (2,4) re2/ad10/cs /p2b (4) re0/ad8/rd /p2d (4) re1/ad9/wr /p2c (4) osc2/clko/ra6 portf rf6/an11 rf7/ss rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf0/an5 rf1/an6/c2out rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd rc1/t1osi/eccp2 (1) /p2a (1) v dd , v ss mclr (3) eccp2 eccp3 eccp1 mclr /v pp /rg5 (3) rd7/ad7/psp7: bor ad15:ad0, a19:16 (4) system bus interface data eeprom rd0/ad0/psp0 (4)
? 2005 microchip technology inc. ds39612b-page 11 PIC18F6525/6621/8525/8621 table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x mclr /v pp /rg5 (9) mclr v pp rg5 79 i p i st ? st master clear (input) or programming voltage (output). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki osc1 clki 39 49 i i cmos/st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode; otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). osc2/clko/ra6 osc2 clko ra6 40 50 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/ 8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 12 ? 2005 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 34 i/o i st/od st digital i/o ? open-drain when configured as output. timer0 external clock input. ra5/an4/lvdin ra5 an4 lvdin 27 33 i/o i i ttl analog analog digital i/o. analog input 4. low-voltage detect input. ra6 see the osc2/clko/ra6 pin. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
? 2005 microchip technology inc. ds39612b-page 13 PIC18F6525/6621/8525/8621 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 48 58 i/o i i ttl st st digital i/o. external interrupt 0. pwm fault input for eccp1. rb1/int1 rb1 int1 47 57 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 56 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/eccp2/p2a rb3 int3 eccp2 (1) p2a (1) 45 55 i/o i/o i/o o ttl st st ? digital i/o. external interrupt 3. enhanced capture 2 input, compare 2 output, pwm2 output. eccp2 output p2a. rb4/kbi0 rb4 kbi0 44 54 i/o i ttl st digital i/o. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 43 53 i/o i i/o ttl st st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 52 i/o i i/o ttl st st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock. rb7/kbi3/pgd rb7 kbi3 pgd 37 47 i/o i i/o ttl st st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/ 8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 14 ? 2005 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 (2) p2a (2) 29 35 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. enhanced capture 2 input, compare 2 output, pwm 2 output. eccp2 output p2a. rc2/eccp1/p1a rc2 eccp1 p1a 33 43 i/o i/o o st st ? digital i/o. enhanced capture 1 input, compare 1 output, pwm 1 output. eccp1 output p1a. rc3/sck/scl rc3 sck scl 34 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 35 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 36 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 37 i/o o i/o st ? st digital i/o. usart1 asynchronous transmit. usart1 synchronous clock (see rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 38 i/o i i/o st st st digital i/o. usart1 asynchronous receive. usart1 synchronous data (see tx1/ck1). table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
? 2005 microchip technology inc. ds39612b-page 15 PIC18F6525/6621/8525/8621 portd is a bidirectional i/o port. these pins have ttl input buffers when external memory is enabled. rd0/ad0/psp0 rd0 ad0 (3) psp0 58 72 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 (3) psp1 55 69 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 (3) psp2 54 68 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 (3) psp3 53 67 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4 rd4 ad4 (3) psp4 52 66 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 4. parallel slave port data. rd5/ad5/psp5 rd5 ad5 (3) psp5 51 65 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 5. parallel slave port data. rd6/ad6/psp6 rd6 ad6 (3) psp6 50 64 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 6. parallel slave port data. rd7/ad7/psp7 rd7 ad7 (3) psp7 49 63 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 7. parallel slave port data. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/ 8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 16 ? 2005 microchip technology inc. porte is a bidirectional i/o port. re0/ad8/rd /p2d re0 ad8 (3) rd p2d 24 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 8. read control for parallel slave port. eccp2 output p2d. re1/ad9/wr /p2c re1 ad9 (3) wr p2c 13 i/o i/o i o st ttl ttl st digital i/o. external memory address/data 9. write control for parallel slave port. eccp2 output p2c. re2/ad10/cs /p2b re2 ad10 (3) cs p2b 64 78 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 10. chip select control for parallel slave port. eccp2 output p2b. re3/ad11/p3c re3 ad11 (3) p3c (4) 63 77 i/o i/o o st ttl ? digital i/o. external memory address/data 11. eccp3 output p3c. re4/ad12/p3b re4 ad12 (3) p3b (4) 62 76 i/o i/o o st ttl ? digital i/o. external memory address/data 12. eccp3 output p3b. re5/ad13/p1c re5 ad13 (3) p1c (4) 61 75 i/o i/o o st ttl ? digital i/o. external memory address/data 13. eccp1 output p1c. re6/ad14/p1b re6 ad14 (3) p1b (4) 60 74 i/o i/o o st ttl ? digital i/o. external memory address/data 14. eccp1 output p1b. re7/ad15/eccp2/p2a re7 ad15 (3) eccp2 (5) p2a (5) 59 73 i/o i/o i/o o st ttl st ? digital i/o. external memory address/data 15. enhanced capture 2 input, compare 2 output, pwm 2 output. eccp2 output p2a. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
? 2005 microchip technology inc. ds39612b-page 17 PIC18F6525/6621/8525/8621 portf is a bidirectional i/o port. rf0/an5 rf0 an5 18 24 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 17 23 i/o i o st analog st digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 18 i/o i o st analog st digital i/o. analog input 7. comparator 1 output. rf3/an8 rf1 an8 15 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf1 an9 14 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf1 an10 cv ref 13 15 i/o i o st analog analog digital i/o. analog input 10. comparator v ref output. rf6/an11 rf6 an11 12 14 i/o i st analog digital i/o. analog input 11. rf7/ss rf7 ss 11 13 i/o i st ttl digital i/o. spi? slave select input. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/ 8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 18 ? 2005 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 35 i/o i/o o st st ? digital i/o. enhanced capture 3 input, compare 3 output, pwm 3 output. eccp3 output p3a. rg1/tx2/ck2 rg1 tx2 ck2 46 i/o o i/o st ? st digital i/o. usart2 asynchronous transmit. usart2 synchronous clock (see rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 57 i/o i i/o st st st digital i/o. usart2 asynchronous receive. usart2 synchronous data (see tx2/ck2). rg3/ccp4/p3d rg3 ccp4 p3d 68 i/o i/o o st st ? digital i/o. capture 4 input, compare 4 output, pwm 4 output. eccp3 output p3d. rg4/ccp5/p1d rg4 ccp5 p1d 810 i/o i/o o st st ? digital i/o. capture 5 input, compare 5 output, pwm 5 output. eccp1 output p1d. rg5 7 9 ? ? see mclr /v pp /rg5 pin. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
? 2005 microchip technology inc. ds39612b-page 19 PIC18F6525/6621/8525/8621 porth is a bidirectional i/o port (6) . rh0/a16 rh0 a16 ?79 i/o o st ttl digital i/o. external memory address 16. rh1/a17 rh1 a17 ?80 i/o o st ttl digital i/o. external memory address 17. rh2/a18 rh2 a18 ?1 i/o o st ttl digital i/o. external memory address 18. rh3/a19 rh3 a19 ?2 i/o o st ttl digital i/o. external memory address 19. rh4/an12/p3c rh4 an12 p3c (7) ?22 i/o i o st analog ? digital i/o. analog input 12. eccp3 output p3c. rh5/an13/p3b rh5 an13 p3b (7) ?21 i/o i o st analog ? digital i/o. analog input 13. eccp3 output p3b. rh6/an14/p1c rh6 an14 p1c (7) ?20 i/o i o st analog ? digital i/o. analog input 14. eccp1 output p1c. rh7/an15/p1b rh7 an15 p1b (7) ?19 i/o i o st analog ? digital i/o. analog input 15. eccp1 output p1b. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/ 8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 20 ? 2005 microchip technology inc. portj is a bidirectional i/o port (6) . rj0/ale rj0 ale ?62 i/o o st ttl digital i/o. external memory address latch enable. rj1/oe rj1 oe ?61 i/o o st ttl digital i/o. external memory output enable. rj2/wrl rj2 wrl ?60 i/o o st ttl digital i/o. external memory write low control. rj3/wrh rj3 wrh ?59 i/o o st ttl digital i/o. external memory write high control. rj4/ba0 rj4 ba0 ?39 i/o o st ttl digital i/o. system bus byte address 0 control. rj5/ce rj5 ce ?40 i/o o st ttl digital i/o external memory access indicator. rj6/lb rj6 lb ?41 i/o o st ttl digital i/o. external memory low byte select. rj7/ub rj7 ub ?42 i/o o st ttl digital i/o. external memory high byte select. v ss 9, 25, 41, 56 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 10, 26, 38, 57 12, 32, 48, 71 p ? positive supply for logic and i/o pins. av ss (8) 20 26 p ? ground reference for analog modules. av dd (8) 19 25 p ? positive supply for analog modules. table 1-2: PIC18F6525/6621/8525/8621 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pic18f6x2x pic18f8x2x legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a in pic18f8525/8621 devices when ccp2mx (config3h<0>) is not set (all program memory modes except microcontroller). 2: default assignment for eccp2/p2a when ccp2mx is set (all devices). 3: external memory interface functions are only available on pic18f8525/8621 devices. 4: default assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is set and for all PIC18F6525/6621 devices. 5: alternate assignment for eccp2/p2a in pic18f8525/8621 dev ices when ccp2mx is not set (microcontroller mode). 6: porth and portj (and their multiplexed functions) are only available on pic18f8525/8621 devices. 7: alternate assignment for p1b/p1c/p3b/p3c for pic18f8525/8621 devices when eccpmx (config3h<1>) is not set. 8: av dd must be connected to a positive supply and av ss must be connected to a ground refe rence for proper operation of the part in user or icsp? modes. see parameter d001 for details. 9: rg5 is multiplexed with mclr and is only available when the mclr resets are disabled.
? 2005 microchip technology inc. ds39612b-page 21 PIC18F6525/6621/8525/8621 2.0 oscillator configurations 2.1 oscillator types the PIC18F6525/6621/8525/8621 devices can be operated in twelve different oscillator modes. the user can program four configuration bits (fosc3, fosc2, fosc1 and fosc0) to select one of these eight modes: 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. rc external resistor/capacitor 5. ec external clock 6. ecio external clock with i/o pin enabled 7. hs+pll high-speed crystal/resonator with pll enabled 8. rcio external resistor/capacitor with i/o pin enabled 9. ecio+spll external clock with software controlled pll 10. ecio+pll external clock with pll and i/o pin enabled 11. hs+spll high-speed crystal/resonator with software control 12. rcio external resistor/capacitor with i/o pin enabled 2.2 crystal oscillator/ceramic resonators in xt, lp, hs, hs+pll or hs+spll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the PIC18F6525/6621/8525/8621 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs, xt or lp configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. ranges tested: mode freq c1 c2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-68 pf 15-68 pf 68-100 pf 15-68 pf 15-68 pf hs 8.0 mhz 16.0 mhz 10-68 pf 10-22 pf 10-68 pf 10-22 pf these values are for design guidance only. see notes following this table. resonators used: 2 khz 8 mhz 4 mhz 16 mhz note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: when operating below 3v v dd , or when using certain ceramic resonators at any voltage, it may be necessary to use high gain hs mode, try a lower frequency resonator or switch to a crystal oscillator. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components or verify oscillator performance. note 1: see table 2-1 and table 2-2 for recommended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18f6x2x/8x2x r s (2) internal
PIC18F6525/6621/8525/8621 ds39612b-page 22 ? 2005 microchip technology inc. table 2-2: capacitor selection for crystal oscillator an external clock source may also be connected to the osc1 pin in the hs, xt and lp modes as shown in figure 2-2. figure 2-2: external clock input operation (hs, xt or lp oscillator configuration) 2.3 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. further- more, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 2-3 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3: rc oscillator mode the rcio oscillator mode functions like the rc mode except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). ranges tested: mode freq c1 c2 lp 32.0 khz 33 pf 33 pf xt 200 khz 47-68 pf 47-68 pf 1.0 mhz 15 pf 15 pf 4.0 mhz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes following this table. crystals used 32 khz 4 mhz 200 khz 8 mhz 1 mhz 20 mhz note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: r s (see figure 2-1) may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components or verify oscillator performance. osc1 osc2 open clock from ext. system pic18f6x2x/8x2x osc2/clko c ext r ext pic18f6x2x/8x2x osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf
? 2005 microchip technology inc. ds39612b-page 23 PIC18F6525/6621/8525/8621 2.4 external clock input the ec, ecio, ec+pll and ec+spll oscillator modes require an external clock source to be con- nected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in these modes to save current. there is a maximum 1.5 s start-up required after a power-on reset or wake-up from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-4 shows the pin connections for the ec oscillator mode. figure 2-4: external clock input operation (ec configuration) the ecio oscillator mode functions like the ec mode except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-5 shows the pin connections for the ecio oscillator mode. figure 2-5: external clock input operation (ecio configuration) 2.5 phase locked loop (pll) a phase locked loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming oscillator signal by 4. for an input clock frequency of 10 mhz, the internal clock frequency will be multiplied to 40 mhz. this is useful for customers who are concerned with emi due to high-frequency crystals. the pll can only be enabled when the oscillator configuration bits are programmed for high-speed oscillator or external clock mode. if they are programmed for any other mode, the pll is not enabled and the system clock will come directly from osc1. there are two types of pll modes: software controlled pll and configuration bits controlled pll. in software controlled pll mode, PIC18F6525/6621/ 8525/8621 executes at regular clock frequency after all reset conditions. during execution, the application can enable pll and switch to 4x clock frequency operation by setting the pllen bit in the osccon register. in configuration bits controlled pll, the pll operation cannot be changed ?on-the-fly?. to enable or disable it, the controller must either cycle through a power-on reset, or switch the clock source from the main oscillator to the timer1 oscillator and back again (see section 2.6 ?oscillator switching feature? for details). the type of pll is selected by programming fosc<3:0> configuration bits in the config1h configuration register. the oscillator mode is specified during device programming. a pll lock timer is used to ensure that the pll has locked before device execution starts. the pll lock timer has a time-out that is called t pll . figure 2-6: pll block diagram osc1 osc2 f osc /4 clock from ext. system pic18f6x2x/8x2x osc1 i/o (osc2) ra6 clock from ext. system pic18f6x2x/8x2x mux v co divide by 4 pll enable f in f out sysclk phase comparator loop filter
PIC18F6525/6621/8525/8621 ds39612b-page 24 ? 2005 microchip technology inc. 2.6 oscillator switching feature the PIC18F6525/6621/8525/8621 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. for the PIC18F6525/6621/ 8525/8621 devices, this alternate clock source is the timer1 oscillator. if a low-frequency crystal (32 khz, for example) has been attached to the timer1 oscillator pins and the timer1 oscillator has been enabled, the device can switch to a low-power execution mode. figure 2-7 shows a block diagram of the system clock sources. the clock switching feature is enabled by programming the oscillator switching enable (oscsen ) bit in the config1h configuration register to a ? 0 ?. clock switching is disabled in an erased device. see section 12.0 ?timer1 module? for further details of the timer1 oscillator. see section 24.0 ?special features of the cpu? for configuration register details. figure 2-7: device clock sources pic18f6x2x/8x2x t osc 4 x pll t t 1 p t sclk clock source mux t osc /4 t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep timer1 oscillator main oscillator
? 2005 microchip technology inc. ds39612b-page 25 PIC18F6525/6621/8525/8621 2.6.1 system clock switch bit the system clock source switching is performed under software control. the system clock switch bits, scs1:scs0 (osccon<1:0>), control the clock switching. when the scs0 bit is ? 0 ?, the system clock source comes from the main oscillator that is selected by the fosc configuration bits in the config1h configuration register. when the scs0 bit is set, the system clock source will come from the timer1 oscillator. the scs0 bit is cleared on all forms of reset. when the fosc bits are programmed for software pll mode, the scs1 bit can be used to select between primary oscillator/clock and pll output. the scs1 bit will only have an effect on the system clock if the pll is enabled (pllen = 1 ) and locked (lock = 1 ), else it will be forced cleared. when programmed with configuration controlled pll, the scs1 bit will be forced clear. register 2-1: osccon: oscillator control regi ster note: the timer1 oscillator must be enabled and operating to switch the system clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control register (t1con). if the timer1 oscillator is not enabled, then any write to the scs0 bit will be ignored (scs0 bit forced cleared) and the main oscillator will continue to be the system clock source. u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?lockpllen (1) scs1 scs0 (2) bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 lock: phase lock loop lock status bit 1 = phase lock loop output is stable as system clock 0 = phase lock loop output is not stable and output cannot be used as system clock bit 2 pllen: phase lock loop enable bit (1) 1 = enable phase lock loop output as system clock 0 = disable phase lock loop bit 1 scs1: system clock switch bit 1 when pllen and lock bits are set: 1 = use pll output 0 = use primary oscillator/clock input pin when pllen or lock bit is cleared: bit is forced clear. bit 0 scs0: system clock switch bit 0 (2) when oscsen configuration bit = 0 and t1oscen bit = 1 : 1 = switch to timer1 oscillator/clock pin 0 = use primary oscillator/clock input pin when oscsen and t1oscen are in other states: bit is forced clear. note 1: pllen bit is forced set when configured for ecio+pll and hs+pll modes. this bit is writable for ecio+spll and hs+spll modes only; forced cleared for all other oscillator modes. 2: the setting of scs0 = 1 supersedes scs1 = 1 . legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 26 ? 2005 microchip technology inc. 2.6.2 oscillator transitions PIC18F6525/6621/8525/8621 devices contain circuitry to prevent ?glitches? when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switch- ing to. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. a timing diagram indicating the transition from the main oscillator to the timer1 oscillator is shown in figure 2-8. the timer1 oscillator is assumed to be running all the time. after the scs0 bit is set, the processor is frozen at the next occurring q1 cycle. after eight synchronization cycles are counted from the timer1 oscillator, operation resumes. no additional delays are required after the synchronization cycles. figure 2-8: timing diagram for transiti on from osc1 to timer1 oscillator the sequence of events that takes place when switch- ing from the timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. in addition to eight clock cycles of the main oscillator, additional delays may take place. if the main oscillator is configured for an external crystal (hs, xt, lp), then the transition will take place after an oscillator start-up time (t ost ) has occurred. a timing diagram, indicating the transition from the timer1 oscillator to the main oscillator for hs, xt and lp modes, is shown in figure 2-9. figure 2-9: timing for transition between timer1 and osc1 (hs, xt, lp) q3 q2 q1 q4 q3 q2 osc1 internal scs (osccon<0>) program pc + 2 pc note: t dly is the delay from scs high to first count of transition circuit. q1 t1osi q4 q1 q1 t scs clock counter system q2 q3 q4 q1 t dly t t 1 p t osc 2 1 34 5678 pc + 4 q3 q3 q4 q1 q2 q3 q4 q1 q2 osc1 internal scs (osccon<0>) program pc pc + 2 note: t ost = 1024 t osc (drawing not to scale). t1osi system clock t ost q1 pc + 6 t t 1 p t osc t scs 12345678 counter
? 2005 microchip technology inc. ds39612b-page 27 PIC18F6525/6621/8525/8621 if the main oscillator is configured for hs mode with pll active, an oscillator start-up time (t ost ) plus an additional pll time-out (t pll ) will occur. the pll time- out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram, indicating the transition from the timer1 oscillator to the main oscillator for hs+pll mode, is shown in figure 2-10. figure 2-10: timing for transition between timer1 and osc1 (hs with pll active, scs1 = 1 ) if the main oscillator is configured for ec mode with pll active, only pll time-out (t pll ) will occur. the pll time- out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram, indicating the transition from the timer1 oscillator to the main oscillator for ec with pll active, is shown in figure 2-11. figure 2-11: timing for transition between timer1 and osc1 (ec with pll active, scs1 = 1 ) q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note: t ost = 1024 t osc (drawing not to scale). t1osi clock t ost q3 pc + 4 t pll t osc t t 1 p t scs q4 pll clock input 1 23 4 56 78 q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 t1osi clock q3 pc + 4 t pll t osc t t 1 p t scs q4 pll clock input 12345678
PIC18F6525/6621/8525/8621 ds39612b-page 28 ? 2005 microchip technology inc. if the main oscillator is configured in the rc, rcio, ec or ecio modes, there is no oscillator start-up time-out. operation will resume after eight cycles of the main oscillator have been counted. a timing diagram, indi- cating the transition from the timer1 oscillator to the main oscillator for rc, rcio, ec and ecio modes, is shown in figure 2-12. figure 2-12: timing for transition between timer1 and osc1 (rc, ec) 2.7 effects of sleep mode on the on-chip oscillator when the device executes a sleep instruction, the on- chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset, or through an interrupt. table 2-3: osc1 and osc2 pin states in sleep mode 2.8 power-up delays power-up delays are controlled by two timers so that no external reset circuitry is required for most applications. the delays ensure that the device is kept in reset until the device power supply and clock are stable. for additional information on reset operation, see section 3.0 ?reset? . the first timer is the power-up timer (pwrt) which optionally provides a fixed delay of 72 ms (nominal) on power-up only (por and bor). the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. with the pll enabled (hs+pll and ec+pll oscillator mode), the time-out sequence following a power-on reset is different from other oscillator modes. the time-out sequence is as follows: first, the pwrt time- out is invoked after a por time delay has expired. then, the oscillator start-up timer (ost) is invoked. however, this is still not a sufficient amount of time to allow the pll to lock at high frequencies. the pwrt timer is used to provide an additional fixed 2 ms (nominal) time-out to allow the pll ample time to lock to the incoming clock frequency. q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs (osccon<0>) program pc pc + 2 note: rc oscillator mode assumed. pc + 4 t1osi clock q4 t t 1 p t osc t scs 12 345 678 counter oscillator mode osc1 pin osc2 pin rc floating, external resistor should pull high at logic low rcio floating, external resistor should pull high configured as porta, bit 6 ecio floating configured as porta, bit 6 ec floating at logic low lp, xt and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 3-1 in section 3.0 ?reset? for time-outs due to sleep and mclr reset.
? 2005 microchip technology inc. ds39612b-page 29 PIC18F6525/6621/8525/8621 3.0 reset the PIC18F6525/6621/8525/8621 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? on power-on reset, mclr , wdt reset, brown- out reset, mclr reset during sleep and by the reset instruction. most registers are not affected by a wdt wake-up since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor , are set or cleared differently in different reset situations as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. the mclr pin is not driven low by any internal resets, including the wdt. figure 3-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_rese t 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. 2: see table 3-1 for time-out situations. brown-out reset bor reset instruction stack pointer stack full/underflow reset
PIC18F6525/6621/8525/8621 ds39612b-page 30 ? 2005 microchip technology inc. 3.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por circuitry, tie the mclr pin through a 1 k ? to 10 k ? resistor to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. figure 3-2: external power-on reset circuit (for slow v dd power-up) 3.2 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter 33) only on power-up from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt?s time delay allows v dd to rise to an acceptable level. a configuration bit is provided to enable/disable the pwrt. the power-up time delay will vary from chip-to-chip due to v dd , temperature and process variation. see dc parameter 33 for details. 3.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delays after the pwrt delay is over (parameter 32). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset, or wake-up from sleep. 3.4 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is different from other oscillator modes. a portion of the power-up timer is used to pro- vide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 3.5 brown-out reset (bor) a configuration bit, bor, can disable (if clear/ programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below parameter d005 for greater than parameter 35, the brown-out situation will reset the chip. a reset may not occur if v dd falls below parameter d005 for less than parameter 35. the chip will remain in brown-out reset until v dd rises above bv dd . if the power-up timer is enabled, it will be invoked after v dd rises above bv dd ; it then will keep the chip in reset for an additional time delay (parameter 33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. 3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired. then, ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, the time-outs will expire if mclr is kept low long enough. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one PIC18F6525/6621/8525/ 8621 device operating in parallel. table 3-2 shows the reset conditions for some special function registers, while table 3-3 shows the reset conditions for all of the registers. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 = 1 k ? to 10 k ? will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18f6x2x/8x2x
? 2005 microchip technology inc. ds39612b-page 31 PIC18F6525/6621/8525/8621 table 3-1: time-out in various situations register 3-1: rcon register bits and positions (1) table 3-2: status bits, their significanc e and the initialization condition for rcon register oscillator configuration power-up (2) brown-out wake-up from sleep or oscillator switch pwrte = 0 pwrte = 1 hs with pll enabled (1) 72 ms + 1024 t osc + 2 ms 1024 t osc + 2 ms 72 ms (2) + 1024 t osc + 2 ms 1024 t osc + 2 ms hs, xt, lp 72 ms + 1024 t osc 1024 t osc 72 ms (2) + 1024 t osc 1024 t osc ec 72 ms 1.5 s72 ms (2) 1.5 s (3) external rc 72 ms ? 72 ms (2) ? note 1: 2 ms is the nominal time required for the 4x pll to lock. 2: 72 ms is the nominal power-up timer delay, if implemented. 3: 1.5 s is the recovery time from sleep. there is no recovery time from oscillator switch. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 note 1: refer to section 4.14 ?rcon register? for bit definitions. condition program counter ri to pd por bor stkful stkunf power-on reset 0000h 111 0 0 u u mclr reset during normal operation 0000h uuu u u u u software reset during normal operation 0000h 0uu u u u u stack full reset during normal operation 0000h uuu u u u 1 stack underflow reset during normal operation 0000h uuu u u 1 u mclr reset during sleep 0000h u10 u u u u wdt reset 0000h 101 u u u u wdt wake-up pc + 2 u00 u u u u brown-out reset 0000h 111 1 0 u u interrupt wake-up from sleep pc + 2 (1) u10 u u u u legend: u = unchanged, x = unknown note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (0008h or 0018h).
PIC18F6525/6621/8525/8621 ds39612b-page 32 ? 2005 microchip technology inc. table 3-3: initialization co nditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu pic18f6x2x pic18f8x2x ---0 0000 ---0 0000 ---0 uuuu (3) tosh pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu (3) tosl pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu (3) stkptr pic18f6x2x pic18f8x2x 00-0 0000 uu-0 0000 uu-u uuuu (3) pclatu pic18f6x2x pic18f8x2x ---0 0000 ---0 0000 ---u uuuu pclath pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu pcl pic18f6x2x pic18f8x2x 0000 0000 0000 0000 pc + 2 (2) tblptru pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu tblptrh pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu tblptrl pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu tablat pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu prodh pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu prodl pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu intcon pic18f6x2x pic18f8x2x 0000 000x 0000 000u uuuu uuuu (1) intcon2 pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu (1) intcon3 pic18f6x2x pic18f8x2x 1100 0000 1100 0000 uuuu uuuu (1) indf0 pic18f6x2x pic18f8x2x n/a n/a n/a postinc0 pic18f6x2x pic18f8x2x n/a n/a n/a postdec0 pic18f6x2x pic18f8x2x n/a n/a n/a preinc0 pic18f6x2x pic18f8x2x n/a n/a n/a plusw0 pic18f6x2x pic18f8x2x n/a n/a n/a fsr0h pic18f6x2x pic18f8x2x ---- 0000 ---- 0000 ---- uuuu fsr0l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu wreg pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu indf1 pic18f6x2x pic18f8x2x n/a n/a n/a postinc1 pic18f6x2x pic18f8x2x n/a n/a n/a postdec1 pic18f6x2x pic18f8x2x n/a n/a n/a preinc1 pic18f6x2x pic18f8x2x n/a n/a n/a plusw1 pic18f6x2x pic18f8x2x n/a n/a n/a fsr1h pic18f6x2x pic18f8x2x ---- 0000 ---- 0000 ---- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: bit 6 of porta, lata and trisa are not available on all devices. when unimplemented, they are read ? 0 ?. 7: if mclr function is disabled, portg<5> is a read-only bit. 8: enabled only in microcontroller mode for pic18f8525/8621 devices. 9: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode.
? 2005 microchip technology inc. ds39612b-page 33 PIC18F6525/6621/8525/8621 fsr1l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu bsr pic18f6x2x pic18f8x2x ---- 0000 ---- 0000 ---- uuuu indf2 pic18f6x2x pic18f8x2x n/a n/a n/a postinc2 pic18f6x2x pic18f8x2x n/a n/a n/a postdec2 pic18f6x2x pic18f8x2x n/a n/a n/a preinc2 pic18f6x2x pic18f8x2x n/a n/a n/a plusw2 pic18f6x2x pic18f8x2x n/a n/a n/a fsr2h pic18f6x2x pic18f8x2x ---- 0000 ---- 0000 ---- uuuu fsr2l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu status pic18f6x2x pic18f8x2x ---x xxxx ---u uuuu ---u uuuu tmr0h pic18f6x2x pic18f8x2x 0000 0000 uuuu uuuu uuuu uuuu tmr0l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu t0con pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu osccon pic18f6x2x pic18f8x2x ---- 0000 ---- 0000 ---- uuuu lvdcon pic18f6x2x pic18f8x2x --00 0101 --00 0101 --uu uuuu wdtcon pic18f6x2x pic18f8x2x ---- ---0 ---- ---0 ---- ---u rcon (4) pic18f6x2x pic18f8x2x 0--1 11qq 0--1 qquu u--1 qquu tmr1h pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu tmr1l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu t1con pic18f6x2x pic18f8x2x 0-00 0000 u-uu uuuu u-uu uuuu tmr2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu pr2 pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu t2con pic18f6x2x pic18f8x2x -000 0000 -000 0000 -uuu uuuu sspbuf pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu sspadd pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu sspstat pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu sspcon1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu sspcon2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu adresh pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu adresl pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: bit 6 of porta, lata and trisa are not available on all devices. when unimplemented, they are read ? 0 ?. 7: if mclr function is disabled, portg<5> is a read-only bit. 8: enabled only in microcontroller mode for pic18f8525/8621 devices. 9: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode.
PIC18F6525/6621/8525/8621 ds39612b-page 34 ? 2005 microchip technology inc. adcon0 pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu adcon1 pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu adcon2 pic18f6x2x pic18f8x2x 0-00 0000 0-00 0000 u-uu uuuu ccpr1h pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccp1con pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu ccpr2h pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccp2con pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu ccpr3h pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccpr3l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu ccp3con pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eccp1as pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu cvrcon pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu cmcon pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu tmr3h pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu tmr3l pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu t3con pic18f6x2x pic18f8x2x 0000 0000 uuuu uuuu uuuu uuuu pspcon (8) pic18f6x2x pic18f8x2x 0000 ---- 0000 ---- uuuu ---- spbrg1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu rcreg1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu txreg1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu txsta1 pic18f6x2x pic18f8x2x 0000 0010 0000 0010 uuuu uuuu rcsta1 pic18f6x2x pic18f8x2x 0000 000x 0000 000x uuuu uuuu eeadrh pic18f6x2x pic18f8x2x ---- --00 ---- --00 ---- --uu eeadr pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eedata pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eecon2 pic18f6x2x pic18f8x2x ---- ---- ---- ---- ---- ---- eecon1 pic18f6x2x pic18f8x2x xx-0 x000 uu-0 u000 uu-u u000 table 3-3: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: bit 6 of porta, lata and trisa are not available on all devices. when unimplemented, they are read ? 0 ?. 7: if mclr function is disabled, portg<5> is a read-only bit. 8: enabled only in microcontroller mode for pic18f8525/8621 devices. 9: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode.
? 2005 microchip technology inc. ds39612b-page 35 PIC18F6525/6621/8525/8621 ipr3 pic18f6x2x pic18f8x2x --11 1111 --11 1111 --uu uuuu pir3 pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu pie3 pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu ipr2 pic18f6x2x pic18f8x2x -1-1 1111 -1-1 1111 -u-u uuuu pir2 pic18f6x2x pic18f8x2x -0-0 0000 -0-0 0000 -u-u uuuu (1) pie2 pic18f6x2x pic18f8x2x -0-0 0000 -0-0 0000 -u-u uuuu ipr1 pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu pir1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu (1) pie1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu memcon (9) pic18f6x2x pic18f8x2x 0-00 --00 0-00 --00 u-uu --uu trisj pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trish pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trisg pic18f6x2x pic18f8x2x ---1 1111 ---1 1111 ---u uuuu trisf pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trise pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trisd pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trisc pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trisb pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu trisa (5,6) pic18f6x2x pic18f8x2x -111 1111 (5) -111 1111 (5) -uuu uuuu (5) latj pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu lath pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu latg pic18f6x2x pic18f8x2x ---x xxxx ---u uuuu ---u uuuu latf pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu late pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu latd pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu latc pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu latb pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu lata (5,6) pic18f6x2x pic18f8x2x -xxx xxxx (5) -uuu uuuu (5) -uuu uuuu (5) portj pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu porth pic18f6x2x pic18f8x2x 0000 xxxx 0000 uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: bit 6 of porta, lata and trisa are not available on all devices. when unimplemented, they are read ? 0 ?. 7: if mclr function is disabled, portg<5> is a read-only bit. 8: enabled only in microcontroller mode for pic18f8525/8621 devices. 9: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode.
PIC18F6525/6621/8525/8621 ds39612b-page 36 ? 2005 microchip technology inc. portg (7) pic18f6x2x pic18f8x2x --xx xxxx --uu uuuu --uu uuuu portf pic18f6x2x pic18f8x2x x000 0000 u000 0000 uuuu uuuu porte pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu portd pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu portc pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu portb pic18f6x2x pic18f8x2x xxxx xxxx uuuu uuuu uuuu uuuu porta (5,6) pic18f6x2x pic18f8x2x -x0x 0000 (5) -u0u 0000 (5) -uuu uuuu (5) spbrgh1 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu baudcon1 pic18f6x2x pic18f8x2x -1-0 0-00 -1-0 0-00 -u-u u-uu spbrgh2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu baudcon2 pic18f6x2x pic18f8x2x -1-0 0-00 -1-0 0-00 -u-1 u-uu eccp1del pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu tmr4 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu pr4 pic18f6x2x pic18f8x2x 1111 1111 1111 1111 uuuu uuuu t4con pic18f6x2x pic18f8x2x -000 0000 -000 0000 -uuu uuuu ccpr4h pic18f6x2x pic18f8x2x xxxx xxxx xxxx xxxx uuuu uuuu ccpr4l pic18f6x2x pic18f8x2x xxxx xxxx xxxx xxxx uuuu uuuu ccp4con pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu ccpr5h pic18f6x2x pic18f8x2x xxxx xxxx xxxx xxxx uuuu uuuu ccpr5l pic18f6x2x pic18f8x2x xxxx xxxx xxxx xxxx uuuu uuuu ccp5con pic18f6x2x pic18f8x2x --00 0000 --00 0000 --uu uuuu spbrg2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu rcreg2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu txreg2 pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu txsta2 pic18f6x2x pic18f8x2x 0000 0010 0000 0010 uuuu uuuu rcsta2 pic18f6x2x pic18f8x2x 0000 000x 0000 000x uuuu uuuu eccp3as pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eccp3del pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eccp2as pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu eccp2del pic18f6x2x pic18f8x2x 0000 0000 0000 0000 uuuu uuuu table 3-3: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ?. 6: bit 6 of porta, lata and trisa are not available on all devices. when unimplemented, they are read ? 0 ?. 7: if mclr function is disabled, portg<5> is a read-only bit. 8: enabled only in microcontroller mode for pic18f8525/8621 devices. 9: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode.
? 2005 microchip technology inc. ds39612b-page 37 PIC18F6525/6621/8525/8621 figure 3-3: time-out sequence on power-up (mclr tied to v dd via 1 k ? resistor) figure 3-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
PIC18F6525/6621/8525/8621 ds39612b-page 38 ? 2005 microchip technology inc. figure 3-6: slow rise time (mclr tied to v dd via 1 k ? resistor) figure 3-7: time-out sequence on por w/pll enabled (mclr tied to v dd via 1 k ? resistor) v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr i nternal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer.
? 2005 microchip technology inc. ds39612b-page 39 PIC18F6525/6621/8525/8621 4.0 memory organization there are three memory blocks in PIC18F6525/6621/ 8525/8621 devices. they are: program memory data ram data eeprom data and program memory use separate busses which allow for concurrent access of these blocks. additional detailed information for flash program memory and data eeprom is provided in section 5.0 ?flash program memory? and section 7.0 ?data eeprom memory? , respectively. in addition to on-chip flash, the pic18f8525/8621 devices are also capable of accessing external program memory through an external memory bus. depending on the selected operating mode (discussed in section 4.1.1 ?PIC18F6525/6621/8525/8621 program memory modes? ), the controllers may access either internal or external program memory exclusively, or both internal and external memory in selected blocks. additional information on the external memory interface is provided in section 6.0 ?external memory interface? . 4.1 program memory organization a 21-bit program counter is capable of addressing the 2-mbyte program memory space. accessing a location between the physically implemented memory and the 2-mbyte address will cause a read of all ? 0 ?s (a nop instruction). the PIC18F6525 and pic18f8525 each have 48 kbytes of on-chip flash memory, while the pic18f6621 and pic18f8621 have 64 kbytes of flash. this means that pic18fx525 devices can store inter- nally up to 24,576 single-word instructions and pic18fx621 devices can store up to 32,768 single-word instructions. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. figure 4-1 shows the program memory map for pic18fx525 devices, while figure 4-2 shows the program memory map for pic18fx621 devices. 4.1.1 PIC18F6525/6621/8525/8621 program memory modes pic18f8525/8621 devices differ significantly from their pic18 predecessors in their utilization of program memory. in addition to available on-chip flash program memory, these controllers can also address up to 2 mbytes of external program memory through the external memory interface. there are four distinct operating modes available to the controllers: microprocessor (mp) microprocessor with boot block (mpbb) extended microcontroller (emc) microcontroller (mc) the program memory mode is determined by setting the two least significant bits of the config3l configuration byte register as shown in register 4-1 (see section 24.1 ?configuration bits? for additional details on the device configuration bits). the program memory modes operate as follows: the microprocessor mode permits access only to external program memory; the contents of the on-chip flash memory are ignored. the 21-bit program counter permits access to a 2-mbyte linear program memory space. the microprocessor with boot block mode accesses on-chip flash memory from addresses 000000h to 0007ffh. above this, external program memory is accessed all the way up to the 2-mbyte limit. program execution automatically switches between the two memories as required. the microcontroller mode accesses only on-chip flash memory. attempts to read above the physical limit of the on-chip flash (bfffh for the pic18fx525, ffffh for the pic18fx621) causes a read of all ? 0 ?s (a nop instruction). the microcontroller mode is also the only operating mode available to PIC18F6525/6621 devices. the extended microcontroller mode allows access to both internal and external program memories as a single block. the device can access its entire on-chip flash memory; above this, the device accesses external program memory up to the 2-mbyte program space limit. as with boot block mode, execution automatically switches between the two memories as required. in all modes, the microcontroller has complete access to data ram and eeprom. figure 4-3 compares the memory maps of the different program memory modes. the differences between on-chip and external memory access limitations are more fully explained in table 4-1.
PIC18F6525/6621/8525/8621 ds39612b-page 40 ? 2005 microchip technology inc. figure 4-1: internal program memory map and stack for pic18fx525 figure 4-2: internal program memory map and stack for pic18fx621 table 4-1: memory access for pic18f8525/8621 program memory modes pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 000000h 000018h on-chip flash program memory high priority interrupt vector 000008h user memory space 1fffffh 00c000h 00bfffh read ? 0 ? 200000h pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 000000h 000018h 010000h 00ffffh on-chip flash program memory high priority interrupt vector 000008h user memory space read ? 0 ? 1fffffh 200000h operating mode internal program memory external program memory execution from table read from table write to execution from table read from table write to microprocessor no access no access no access yes yes yes microprocessor w/boot block ye s yes yes yes yes yes microcontroller yes yes yes no access no access no access extended microcontroller ye s yes yes yes yes yes
? 2005 microchip technology inc. ds39612b-page 41 PIC18F6525/6621/8525/8621 register 4-1: config3l: config uration register 3 low figure 4-3: memory maps for PIC18F6525/6621/8525/8621 program memory modes r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 wait ? ? ? ? ?pm1pm0 bit 7 bit 0 bit 7 wait: external bus data wait enable bit 1 = wait selections unavailable, device will not wait 0 = wait programmed by wait1 and wait0 bits of memcom register (memcom<5:4>) bit 6-2 unimplemented: read as ? 0 ? bit 1-0 pm1:pm0: processor data memory mode select bits 11 = microcontroller mode 10 = microprocessor mode (1) 01 = microcontroller with boot block mode (1) 00 = extended microcontroller mode (1) note 1: this mode is available only on pic18f8525/8621 devices. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value after erase ?1? = bit is set ?0? = bit is cleared x = bit is unknown microprocessor mode (3) 000000h 1fffffh external program memory external program memory 1fffffh 000000h on-chip program memory extended microcontroller mode (3) microcontroller mode 000000h external on-chip program space execution on-chip program memory 1fffffh reads 000800h 1fffffh 0007ffh microprocessor with boot block mode (3) 000000h on-chip program memory external program memory memory flash on-chip program memory (no access) ? 0 ?s 010000h (2) 00ffffh (2) external on-chip memory flash on-chip flash external on-chip memory flash 00bfffh (1) 00c000h (1) 00ffffh (2) 00bfffh (1) 010000h (2) 00c000h (1) note 1: pic18f8525 and PIC18F6525. 2: pic18f8621 and pic18f6621. 3: this mode is available only on pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 42 ? 2005 microchip technology inc. 4.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return , retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all resets. there is no ram associated with stack pointer 00000b . this is only a reset value. during a call type instruction causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the contents of the pc. during a return type instruction causing a pop from the stack, the contents of the ram location pointed to by the stkptr register are transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through sfr registers. data can also be pushed to, or popped from the stack using the top-of- stack sfrs. status bits indicate if the stack pointer is at or beyond the 31 levels provided. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl, hold the contents of the stack location pointed to by the stkptr register. this allows users to implement a software stack if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations. 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. register 4-2 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be ? 0 ?. the user may read and write the stack pointer value. this feature can be used by a real-time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack overflow reset enable) configuration bit. refer to section 25.0 ?instruction set summary? for a description of the device configuration bits. if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to ? 0 ?. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at ? 0 ?. the stkunf bit will remain set until cleared in software or a por occurs. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken.
? 2005 microchip technology inc. ds39612b-page 43 PIC18F6525/6621/8525/8621 register 4-2: stkptr: stack pointer register figure 4-4: return address stack and associated registers 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the current pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the ability to pull the tos value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the pop instruction. the pop instruction discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled by programming the stvren configuration bit. when the stvren bit is disabled, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. when the stvren bit is enabled, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are only cleared by the user software or a power-on reset. r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 can only be cleared in user software or by a por. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 00011 0x001a34 11111 11110 11101 00010 00001 00000 00010 return address stack top-of-stack 0x000d58 tosl tosh tosu 0x34 0x1a 0x00 stkptr<4:0>
PIC18F6525/6621/8525/8621 ds39612b-page 44 ? 2005 microchip technology inc. 4.3 fast register stack a ?fast interrupt return? option is available for interrupts. a fast register stack is provided for the status, wreg and bsr registers and is only one in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the registers are then loaded back into the working registers if the fast return instruction is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. if high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide. the low byte is called the pcl register; this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<15:8> bits and is not directly readable or writable; updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable; updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of the pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call , rcall , goto and program branch instruc- tions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be transferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the program counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1 ?computed goto? ). 4.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register (ir) in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 4-5. figure 4-5: clock/ instruction cycle call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock
? 2005 microchip technology inc. ds39612b-page 45 PIC18F6525/6621/8525/8621 4.6 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register? (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). example 4-2: instruction pipeline flow 4.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). figure 4-6 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 4.4 ?pcl, pclath and pclatu? ). the call and goto instructions have an absolute program memory address embedded into the instruction. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1> which accesses the desired byte address in program memory. instruction #2 in figure 4-6 shows how the instruction ? goto 000006h ? is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction represents the number of single-word instructions that the pc will be offset by. section 25.0 ?instruction set summary? provides further details of the instruction set. figure 4-6: instructions in program memory all instructions are single-cycle except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 000006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h
PIC18F6525/6621/8525/8621 ds39612b-page 46 ? 2005 microchip technology inc. 4.7.1 two-word instructions the PIC18F6525/6621/8525/8621 devices have four two-word instructions: movff , call , goto and lfsr . the second word of these instructions has the 4 msbs set to ? 1 ?s and is a special kind of nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is executed, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that changes the pc. a program example that demonstrates this concept is shown in example 4-3. refer to section 25.0 ?instruction set summary? for further details of the instruction set. example 4-3: two-word instructions 4.8 look-up tables look-up tables are implemented two ways. these are: computed goto table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a look-up table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table before exe- cuting a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw 0xnn instructions that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 4-4: computed goto using an offset value case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand becomes nop 0010 0100 0000 0000 addwf reg3 ; continue code note: the addwf pcl instruction does not update pclath and pclatu. a read operation on pcl must be performed to update pclath and pclatu. main: org 0x0000 movlw 0x00 call table ? org 0x8000 table movf pcl, f ; a simple read of pcl will update pclath, pclatu rlncf w, w ; multiply by 2 to get correct offset in table addwf pcl ; add the modified offset to force jump into table retlw ?a? retlw ?b? retlw ?c? retlw ?d? retlw ?e? end
? 2005 microchip technology inc. ds39612b-page 47 PIC18F6525/6621/8525/8621 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. look-up table data may be stored 2 bytes per program word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to program memory. data is transferred to/from program memory, one byte at a time. a description of the table read/table write operation is shown in section 5.0 ?flash program memory? . 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 4-7 shows the data memory organization for the PIC18F6525/6621/8525/8621 devices. the data memory map is divided into 16 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratch pad operations in the user?s appli- cation. the sfrs start at the last location of bank 15 (0fffh) and extend downwards. any remaining space beyond the sfrs in the bank may be implemented as gprs. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ?s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of a file select register (fsrn) and a corresponding indirect file operand (indfn). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 4.10 ?access bank? provides a detailed description of the access ram. 4.9.1 general purpose register file the register file can be accessed either directly or indirectly. indirect addressing operates using a file select register and corresponding indirect file operand. the operation of indirect addressing is shown in section 4.12 ?indirect addressing, indf and fsr registers? . enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as general purpose registers by all instructions. the top section of bank 15 (f60h to fffh) contains sfrs. all other banks of data memory contain gprs, starting with bank 0. 4.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 4-2 and table 4-3. the sfrs can be classified into two sets: those asso- ciated with the ?core? function and those related to the peripheral functions. those registers related to the ?core? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripherals whose functions they control. the unused sfr locations are unimplemented and read as ? 0 ?s. the addresses for the sfrs are listed in table 4-2.
PIC18F6525/6621/8525/8621 ds39612b-page 48 ? 2005 microchip technology inc. figure 4-7: data memory map for PIC18F6525/6621/8525/8621 devices bank 0 bank 1 bank 13 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1110 = 1111 060h 05fh f60h fffh 00h 5fh 60h ffh access bank when ?a? = 0 , the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the second 160 bytes are special function registers (from bank 15). when ?a? = 1 , the bsr is used to specify the ram location that the instruction uses. bank 4 bank 3 bank 2 f5fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0011 = 0010 access ram ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gprs gprs gprs gprs sfrs unused access ram high access ram low bank 14 gprs gprs bank 5 to 4ffh 400h dffh 500h e00h = 0100 (sfrs) gprs
? 2005 microchip technology inc. ds39612b-page 49 PIC18F6525/6621/8525/8621 table 4-2: special function register map address name address name address name address name fffh tosu fdfh indf2 (3) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (3) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (3) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (3) fbch ccpr2h f9ch memcon (2) ffbh pclatu fdbh plusw2 (3) fbbh ccpr2l f9bh ? (1) ffah pclath fdah fsr2h fbah ccp2con f9ah trisj (2) ff9h pcl fd9h fsr2l fb9h ccpr3h f99h trish (2) ff8h tblptru fd8h status fb8h ccpr3l f98h trisg ff7h tblptrh fd7h tmr0h fb7h ccp3con f97h trisf ff6h tblptrl fd6h tmr0l fb6h eccp1as f96h trise ff5h tablat fd5h t0con fb5h cvrcon f95h trisd ff4h prodh fd4h ? (1) fb4h cmcon f94h trisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (2) ff0h intcon3 fd0h rcon fb0h pspcon (4) f90h lath (2) fefh indf0 (3) fcfh tmr1h fafh spbrg1 f8fh latg feeh postinc0 (3) fceh tmr1l faeh rcreg1 f8eh latf fedh postdec0 (3) fcdh t1con fadh txreg1 f8dh late fech preinc0 (3) fcch tmr2 fach txsta1 f8ch latd febh plusw0 (3) fcbh pr2 fabh rcsta1 f8bh latc feah fsr0h fcah t2con faah eeadrh f8ah latb fe9h fsr0l fc9h sspbuf fa9h eeadr f89h lata fe8h wreg fc8h sspadd fa8h eedata f88h portj (2) fe7h indf1 (3) fc7h sspstat fa7h eecon2 f87h porth (2) fe6h postinc1 (3) fc6h sspcon1 fa6h eecon1 f86h portg fe5h postdec1 (3) fc5h sspcon2 fa5h ipr3 f85h portf fe4h preinc1 (3) fc4h adresh fa4h pir3 f84h porte fe3h plusw1 (3) fc3h adresl fa3h pie3 f83h portd fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h adcon2 fa0h pie2 f80h porta note 1: unimplemented registers are read as ? 0 ?. 2: this register is not available on PIC18F6525/6621 devices and reads as ? 0 ?. 3: this is not a physical register. 4: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 50 ? 2005 microchip technology inc. address name address name address name address name f7fh spbrgh1 f5fh ? (1) f3fh ? (1) f1fh ? (1) f7eh baudcon1 f5eh ? (1) f3eh ? (1) f1eh ? (1) f7dh spbrgh2 f5dh ? (1) f3dh ? (1) f1dh ? (1) f7ch baudcon2 f5ch ? (1) f3ch ? (1) f1ch ? (1) f7bh ? (1) f5bh ? (1) f3bh ? (1) f1bh ? (1) f7ah ? (1) f5ah ? (1) f3ah ? (1) f1ah ? (1) f79h eccp1del f59h ? (1) f39h ? (1) f19h ? (1) f78h tmr4 f58h ? (1) f38h ? (1) f18h ? (1) f77h pr4 f57h ? (1) f37h ? (1) f17h ? (1) f76h t4con f56h ? (1) f36h ? (1) f16h ? (1) f75h ccpr4h f55h ? (1) f35h ? (1) f15h ? (1) f74h ccpr4l f54h ? (1) f34h ? (1) f14h ? (1) f73h ccp4con f53h ? (1) f33h ? (1) f13h ? (1) f72h ccpr5h f52h ? (1) f32h ? (1) f12h ? (1) f71h ccpr5l f51h ? (1) f31h ? (1) f11h ? (1) f70h ccp5con f50h ? (1) f30h ? (1) f10h ? (1) f6fh spbrg2 f4fh ? (1) f2fh ? (1) f0fh ? (1) f6eh rcreg2 f4eh ? (1) f2eh ? (1) f0eh ? (1) f6dh txreg2 f4dh ? (1) f2dh ? (1) f0dh ? (1) f6ch txsta2 f4ch ? (1) f2ch ? (1) f0ch ? (1) f6bh rcsta2 f4bh ? (1) f2bh ? (1) f0bh ? (1) f6ah eccp3as f4ah ? (1) f2ah ? (1) f0ah ? (1) f69h eccp3del f49h ? (1) f29h ? (1) f09h ? (1) f68h eccp2as f48h ? (1) f28h ? (1) f08h ? (1) f67h eccp2del f47h ? (1) f27h ? (1) f07h ? (1) f66h ? (1) f46h ? (1) f26h ? (1) f06h ? (1) f65h ? (1) f45h ? (1) f25h ? (1) f05h ? (1) f64h ? (1) f44h ? (1) f24h ? (1) f04h ? (1) f63h ? (1) f43h ? (1) f23h ? (1) f03h ? (1) f62h ? (1) f42h ? (1) f22h ? (1) f02h ? (1) f61h ? (1) f41h ? (1) f21h ? (1) f01h ? (1) f60h ? (1) f40h ? (1) f20h ? (1) f00h ? (1) table 4-2: special function register map (continued) note 1: unimplemented registers are read as ? 0 ?. 2: this register is not available on PIC18F6525/6621 devices and reads as ? 0 ?. 3: this is not a physical register. 4: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 51 PIC18F6525/6621/8525/8621 table 4-3: register file summary file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 32, 42 tosh top-of-stack high byte (tos<15:8>) 0000 0000 32, 42 tosl top-of-stack low byte (tos<7:0>) 0000 0000 32, 42 stkptr stkful stkunf ? return stack pointer 00-0 0000 32, 43 pclatu ? ? ? holding register for pc<20:16> ---0 0000 32, 44 pclath holding register for pc<15:8> 0000 0000 32, 44 pcl pc low byte (pc<7:0>) 0000 0000 32, 44 tblptru ? ?bit 21 (2) program memory table pointer upper byte (tblptr<20:16>) --00 0000 32, 69 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 32, 69 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 32, 69 tablat program memory table latch 0000 0000 32, 69 prodh product register high byte xxxx xxxx 32, 85 prodl product regi ster low byte xxxx xxxx 32, 85 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 32, 89 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 32, 90 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 32, 91 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 56 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 56 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 56 preinc0 uses contents of fsr0 to address data memory ? val ue of fsr0 pre-incremented (not a physical register) n/a 56 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ? value of fsr0 offset by value in wreg n/a 56 fsr0h ? ? ? ? indirect data memory address pointer 0 high byte ---- 0000 32, 56 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 32, 56 wreg working register xxxx xxxx 32 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 56 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 56 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 56 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 56 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ? value of fsr1 offset by value in wreg n/a 56 fsr1h ? ? ? ? indirect data memory address pointer 1 high byte ---- 0000 32, 56 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 33, 56 bsr ? ? ? ? bank select register ---- 0000 33, 55 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 56 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 56 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 56 legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as a port pin in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: these registers are unused on PIC18F6525/6621 devices and read as ? 0 ?. 4: rg5 is available only if mclr function is disabled in configuration. 5: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 52 ? 2005 microchip technology inc. preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 56 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ? value of fsr2 offset by value in wreg n/a 56 fsr2h ? ? ? ? indirect data memory address pointer 2 high byte ---- 0000 33, 56 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 33, 56 status ? ? ?novzdcc ---x xxxx 33, 58 tmr0h timer0 register high byte 0000 0000 33, 133 tmr0l timer0 register low byte xxxx xxxx 33, 133 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 33, 131 osccon ? ? ? ? lock pllen scs1 scs0 ---- 0000 25, 33 lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 33, 255 wdtcon ? ? ? ? ? ? ?swdten ---- ---0 33, 267 rcon ipen ? ?ri to pd por bor 0--1 11qq 33, 59, 101 tmr1h timer1 register high byte xxxx xxxx 33, 139 tmr1l timer1 register low byte xxxx xxxx 33, 139 t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 33, 139 tmr2 timer2 register 0000 0000 33, 142 pr2 timer2 period register 1111 1111 33, 142 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 33, 142 sspbuf mssp receive buffer/transmit register xxxx xxxx 33, 181 sspadd mssp address register in i 2 c slave mode. mssp baud rate reload register in i 2 c master mode. 0000 0000 33, 181 sspstat smp cke d/a psr/w ua bf 0000 0000 33, 174 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 33, 175 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 33, 185 adresh a/d result register high byte xxxx xxxx 33, 241 adresl a/d result register low byte xxxx xxxx 33, 241 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 34, 233 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 34, 234 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 34, 235 ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx 34, 172 ccpr1l enhanced capture/compar e/pwm register 1 low byte xxxx xxxx 34, 172 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 34, 157 ccpr2h enhanced capture/compare/pwm register 2 high byte xxxx xxxx 34, 172 ccpr2l enhanced capture/compar e/pwm register 2 low byte xxxx xxxx 34, 172 ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 34, 157 ccpr3h enhanced capture/compare/pwm register 3 high byte xxxx xxxx 34, 172 ccpr3l enhanced capture/compar e/pwm register 3 low byte xxxx xxxx 34, 172 ccp3con p3m1 p3m0 dc3b1 dc2b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 34, 157 eccp1as eccp1ase eccp1as2 eccp1as1 eccp1as0 pss1ac1 pss1ac0 pss1bd1 pss1bd0 0000 0000 34, 169 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 34, 249 table 4-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as a port pin in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: these registers are unused on PIC18F6525/6621 devices and read as ? 0 ?. 4: rg5 is available only if mclr function is disabled in configuration. 5: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 53 PIC18F6525/6621/8525/8621 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 34, 243 tmr3h timer3 register high byte xxxx xxxx 34, 145 tmr3l timer3 register low byte xxxx xxxx 34, 145 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 34, 145 pspcon (5) ibf obf ibov pspmode ? ? ? ? 0000 ---- 34, 129 spbrg1 enhanced usart1 baud rate generator register low byte 0000 0000 34, 217 rcreg1 enhanced usart1 receive register 0000 0000 34, 224 txreg1 enhanced usart1 transmit register 0000 0000 34, 222 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 34, 214 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 34, 215 eeadrh ? ? ? ? ? ? ee addr register high ---- --00 34, 83 eeadr data eeprom address register 0000 0000 34, 83 eedata data eeprom data register 0000 0000 34, 83 eecon2 data eeprom control register 2 (not a physical register) ---- ---- 34, 83 eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 34, 80 ipr3 ? ? rc2ip tx2ip tmr4ip c cp5ip ccp4ip ccp3ip --11 1111 35, 100 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 35, 94 pie3 ? ? rc2ie tx2ie tmr4ie c cp5ie ccp4ie ccp3ie --00 0000 35, 97 ipr2 ?cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 35, 99 pir2 ?cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 35, 93 pie2 ?cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 35, 96 ipr1 pspip (5) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 35, 98 pir1 pspif (5) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 35, 92 pie1 pspie (5) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 35, 95 memcon (3) ebdis ?wait1wait0 ? ?wm1wm0 0-00 --00 35, 71 trisj (3) data direction control register for portj 1111 1111 35, 127 trish (3) data direction control register for porth 1111 1111 35, 124 trisg ? ? ? data direction control register for portg ---1 1111 35, 119 trisf data direction control register for portf 1111 1111 35, 116 trise data direction control register for porte 1111 1111 35, 113 trisd data direction control register for portd 1111 1111 35, 110 trisc data direction control register for portc 1111 1111 35, 108 trisb data direction control register for portb 1111 1111 35, 105 trisa ? trisa6 (1) data direction control register for porta -111 1111 35, 121 latj (3) read portj data latch, write portj data latch xxxx xxxx 35, 127 lath (3) read porth data latch, write porth data latch xxxx xxxx 35, 124 latg ? ? ? read portg data latch, write portg data latch ---x xxxx 35, 121 latf read portf data latch, write portf data latch xxxx xxxx 35, 119 late read porte data latch, write porte data latch xxxx xxxx 35, 116 latd read portd data latch, write portd data latch xxxx xxxx 35, 113 latc read portc data latch, write portc data latch xxxx xxxx 35, 110 latb read portb data latch, write portb data latch xxxx xxxx 35, 108 lata ?lata6 (1) read porta data latch, write porta data latch (1) -xxx xxxx 35, 105 table 4-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as a port pin in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: these registers are unused on PIC18F6525/6621 devices and read as ? 0 ?. 4: rg5 is available only if mclr function is disabled in configuration. 5: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 54 ? 2005 microchip technology inc. portj (3) read portj pins, write portj data latch xxxx xxxx 35, 127 porth (3) read porth pins, write porth data latch 0000 xxxx 35, 124 portg ? ? rg5 (4) read portg pins, write portg data latch --xx xxxx 36, 121 portf read portf pins, write portf data latch x000 0000 36, 119 porte read porte pins, write porte data latch xxxx xxxx 36, 116 portd read portd pins, write portd data latch xxxx xxxx 36, 113 portc read portc pins, write portc data latch xxxx xxxx 36, 110 portb read portb pins, write portb data latch xxxx xxxx 36, 108 porta ?ra6 (1) read porta pins, write porta data latch (1) -x0x 0000 36, 105 spbrgh1 enhanced usart1 baud rate generator register high byte 0000 0000 36, 217 baudcon1 ? rcidl ?sckpbrg16 ? wue abden -1-0 0-00 36, 216 spbrgh2 enhanced usart2 baud rate generator register high byte 0000 0000 36, 217 baudcon2 ? rcidl ?sckpbrg16 ? wue abden -1-0 0-00 36, 216 eccp1del p1rsen p1dc6 p1dc5 p1dc4 p1dc3 p1dc2 p1dc1 p1dc0 0000 0000 36, 168 tmr4 timer4 register 0000 0000 36, 148 pr4 timer4 period register 1111 1111 36, 148 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 36, 147 ccpr4h capture/compare/pwm register 4 high byte xxxx xxxx 36, 153 ccpr4l capture/compare/pwm register 4 low byte xxxx xxxx 36, 153 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 --00 0000 36, 149 ccpr5h capture/compare/pwm register 5 high byte xxxx xxxx 36, 153 ccpr5l capture/compare/pwm register 5 low byte xxxx xxxx 36, 153 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 --00 0000 36, 149 spbrg2 enhanced usart2 baud rate generator register low byte 0000 0000 36, 217 rcreg2 enhanced usart2 receive register 0000 0000 36, 224 txreg2 enhanced usart2 transmit register 0000 0000 36, 222 txsta2 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 36, 222 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 36, 222 eccp3as eccp3ase eccp3as2 eccp3as1 eccp3as0 pss3ac1 pss3ac0 pss3bd1 pss3bd0 0000 0000 36, 169 eccp3del p3rsen p3dc6 p3dc5 p3dc4 p3dc3 p3dc2 p3dc1 p3dc0 0000 0000 36, 168 eccp2as eccp2ase eccp2as2 eccp2as1 eccp2as0 pss2ac1 pss2ac0 pss2bd1 pss2bd0 0000 0000 36, 169 eccp2del p2rsen p2dc6 p2dc5 p2dc4 p2dc3 p2dc2 p2dc1 p2dc0 0000 0000 36, 168 table 4-3: register file summary (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, ? = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as a port pin in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes. 2: bit 21 of the tblptru allows access to the device configuration bits. 3: these registers are unused on PIC18F6525/6621 devices and read as ? 0 ?. 4: rg5 is available only if mclr function is disabled in configuration. 5: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 55 PIC18F6525/6621/8525/8621 4.10 access bank the access bank is an architectural enhancement, which is very useful for c compiler code optimization. the techniques used by the c compiler may also be useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfrs (no banking) the access bank is comprised of the upper 160 bytes in bank 15 (sfrs) and the lower 96 bytes in bank 0. these two sections will be referred to as access ram high and access ram low, respectively. figure 4-7 indicates the access ram areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register or in the access bank. this bit is denoted by the ?a? bit (for access bit). when forced in the access bank (a = 0 ), the last address in access ram low is followed by the first address in access ram high. access ram high maps the special function registers so that these registers can be accessed without any software overhead. this is useful for testing status flags and modifying control bits. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ?s and writes will have no effect. a movlb instruction has been provided in the instruction set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all ? 0 ?s and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr since the 12-bit addresses are embedded into the instruction word. section 4.12 ?indirect addressing, indf and fsr registers? provides a description of indirect address- ing which allows linear addressing of the entire ram space. figure 4-8: direct addressing note 1: for register file map detail, see table 4-2. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h
PIC18F6525/6621/8525/8621 ds39612b-page 56 ? 2005 microchip technology inc. 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. an fsr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-9 shows the operation of indirect addressing. this shows the moving of the value to the data memory address specified by the value of the fsr register. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actually accesses the register pointed to by the file select register, fsr. reading the indf register itself indirectly (fsr = 0 ), will read 00h. writing to the indf register indirectly, results in a no operation ( nop ). the fsr register contains a 12-bit address which is shown in figure 4-10. the indfn register is not a physical register. address- ing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. example 4-5 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 4-5: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12 bits wide. to store the 12 bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address pointed to by fsr0h:fsr0l. a read from indf1 reads the data from the address pointed to by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all ? 0 ?s are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. perform- ing an operation on one of these five registers determines how the fsr will be modified during indirect addressing. when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) ? indfn. auto-decrement fsrn after an indirect access (post-decrement) ? postdecn. auto-increment fsrn after an indirect access (post-increment) ? postincn. auto-increment fsrn before an indirect access (pre-increment) ? preincn. use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) ? pluswn. when using the auto-increment or auto-decrement features, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal ? 0 ?, the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a stack pointer in addition to its uses for table operations in data memory. each fsr has an address associated with it that performs an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the signed value in the wreg register and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an fsr register contains a value that points to one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post-increment/decrement functions. lfsr fsr0, 0x100 ; next clrf postinc0 ; clear indf ; register and ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? goto next ; no, clear next continue ; yes, continue
? 2005 microchip technology inc. ds39612b-page 57 PIC18F6525/6621/8525/8621 figure 4-9: indirect addressing operation figure 4-10: indirect addressing opcode address file address = access of an indirect addressing register fsr instruction executed instruction fetched ram opcode file 12 12 12 bsr<3:0> 8 4 0h fffh note 1: for register file map detail, see table 4-2. data memory (1) indirect addressing fsr register 11 0 0fffh 0000h location select
PIC18F6525/6621/8525/8621 ds39612b-page 58 ? 2005 microchip technology inc. 4.13 status register the status register, shown in register 4-3, contains the arithmetic status of the alu. as with any other sfr, it can be the operand for any instruction. if the status register is the destination for an instruc- tion that affects the z, dc, c, ov or n bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. there- fore, the result of an instruction with the status register as its destination may be different than intended. as an example, clrf status will set the z bit and leave the remaining status bits unchanged (? 000u u1uu ?). it is recommended that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions that do not affect status bits, see the instruction set summaries in table 25-2. register 4-3: status register note: the c and dc bits operate as the borrow and digit borrow bits respectively in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high- or low-order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 59 PIC18F6525/6621/8525/8621 4.14 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. register 4-4: rcon: reset control register note: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 60 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 61 PIC18F6525/6621/8525/8621 5.0 flash program memory the flash program memory is readable, writable and erasable, during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 8 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruc- tion fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 5.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 5-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 5.5 ?writing to flash program memory? . figure 5-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned. figure 5-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr)
PIC18F6525/6621/8525/8621 ds39612b-page 62 ? 2005 microchip technology inc. figure 5-2: table write operation 5.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register eecon2 register tablat register tblptr registers 5.2.1 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit, eepgd, determines if the access will be a program or data eeprom memory access. when clear, any subsequent operations will operate on the data eeprom memory. when set, any subsequent operations will operate on the program memory. control bit, cfgs, determines if the access will be to the configuration/calibration registers or to program memory/data eeprom memory. when set, subsequent operations will operate on configuration registers regardless of eepgd (see section 24.0 ?special features of the cpu? ). when clear, memory selection access is determined by eepgd. the free bit, when set, will allow a program memory erase operation. when the free bit is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal opera- tion. in these situations, the user can check the wrerr bit and rewrite the location. it is necessary to reload the data and address registers (eedata and eeadr) due to reset values of zero. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of eight hold ing registers, the address of which is determined by tblptrl<2:0>. the process for physically writing dat a to the program memory array is discussed in section 5.5 ?writing to flash program memory? . holding registers program memory note: during normal operation, the wrerr bit is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. note: interrupt flag bit, eeif in the pir2 register, is set when the write is complete. it must be cleared in software.
? 2005 microchip technology inc. ds39612b-page 63 PIC18F6525/6621/8525/8621 register 5-1: eecon1 register (address fa6h) r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program/data eeprom error flag bit 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation) 0 = the write operation completed note: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 64 ? 2005 microchip technology inc. 5.2.2 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 5.2.3 tblptr ? table pointer register the table pointer register (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table opera- tion. these operations are shown in table 5-1. these operations on the tblptr only affect the low-order 21 bits. 5.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory into tablat. when a tblwt is executed, the three lsbs of the table pointer register (tblptr<2:0>) determine which of the eight program memory holding registers is written to. when the timed write to program memory (long write) begins, the 19 msbs of the tblptr (tblptr<21:3>) will determine which program memory block of 8 bytes is written to. for more detail, see section 5.5 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer register (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 5-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 5-1: table pointer operations with tblrd and tblwt instructions figure 5-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase ? tblptr<20:6> write ? tblptr<21:3> read ? tblptr<21:0> tblptrl tblptrh tblptru
? 2005 microchip technology inc. ds39612b-page 65 PIC18F6525/6621/8525/8621 5.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 5-4 shows the interface between the internal program memory and the tablat. figure 5-4: reads from flash program memory example 5-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movfw tablat, w ; get data movwf word_odd
PIC18F6525/6621/8525/8621 ds39612b-page 66 ? 2005 microchip technology inc. 5.4 erasing flash program memory the minimum erase block is 32 words or 64 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased. tblptr<5:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash program memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 5.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer register with address of row being erased. 2. set the eecon1 register for the erase operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable writes; set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. re-enable interrupts. example 5-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw aah movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts
? 2005 microchip technology inc. ds39612b-page 67 PIC18F6525/6621/8525/8621 5.5 writing to flash program memory the minimum programming block is 4 words or 8 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 8 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction has to be executed 8 times for each programming operation. all of the table write operations will essentially be short writes because only the holding registers are written. at the end of updating 8 registers, the eecon1 register must be written to, to start the programming operation with a long write. the long write is necessary for programming the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the eeprom on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations. figure 5-5: table writes to flash program memory 5.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer register with address being erased. 4. do the row erase procedure. 5. load table pointer register with address of first byte being written. 6. write the first 8 bytes into the holding registers with auto-increment. 7. set the eecon1 register for the write operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write (about 2 ms using internal timer). 13. re-enable interrupts. 14. repeat steps 6-14 seven times to write 64 bytes. 15. verify the memory (table read). this procedure will require about 18 ms to update one row of 64 bytes of memory. an example of the required code is given in example 5-3. holding register tablat holding register tblptr = xxxxx7 holding register tblptr = xxxxx1 holding register tblptr = xxxxx0 8 8 8 8 write register tblptr = xxxxx2 program memory note: before setting the wr bit, the table pointer address needs to be within the intended address range of the eight bytes in the holding register.
PIC18F6525/6621/8525/8621 ds39612b-page 68 ? 2005 microchip technology inc. example 5-3: writing to flash program memory movlw d'64 ; number of bytes in erase block movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movf tablat, w ; get data movwf postinc0 ; store data decfsz counter ; done? bra read_block ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low movwf fsr0l movlw new_data_low ; update buffer word movwf postinc0 movlw new_data_high movwf indf0 erase_block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw aah movwf eecon2 ; write aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts tblrd*- ; dummy read decrement write_buffer_back movlw 8 ; number of write buffer groups of 8 bytes movwf counter_hi movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l program_loop movlw 8 ; number of bytes in holding register movwf counter write_word_to_hregs movff postinc0, wreg ; get low byte of buffer data ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_word_to_hregs
? 2005 microchip technology inc. ds39612b-page 69 PIC18F6525/6621/8525/8621 example 5-3: writing to flash program memory (continued) 5.5.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 5.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, users can check the wrerr bit and rewrite the location. 5.5.4 protection against spurious writes to protect against spurious writes to flash program memory, the write initiate sequence must also be followed. see section 24.0 ?special features of the cpu? for more detail. 5.6 flash program operation during code protection see section 24.0 ?special features of the cpu? for details on code protection of flash program memory. table 5-2: registers associated with program flash memory program_memory bsf eecon1, eepgd ; point to flash program memory bcf eecon1, cfgs ; access flash program memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw aah movwf eecon2 ; write aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts decfsz counter_hi ; loop until done bra program_loop bcf eecon1, wren ; disable write to memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets tblptru ? ?bit 21 (1) program memory table pointer upper byte (tblptr<20:16>) --00 0000 --00 0000 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 tblptrl program memory table pointer high byte (tblptr<7:0>) 0000 0000 0000 0000 tablat program memory table latch 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u eecon2 eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 ? cmip ?eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 -1-1 1111 pir2 ? cmif ?eeif bclif lvdif tmr3if ccp2if -0-0 0000 -0-0 0000 pie2 ? cmie ?eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 -0-0 0000 legend: x = unknown, u = unchanged, r = reserved, ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access. note 1: bit 21 of the tblptru allows access to device configuration bits.
PIC18F6525/6621/8525/8621 ds39612b-page 70 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 71 PIC18F6525/6621/8525/8621 6.0 external memory interface the external memory interface is a feature of the pic18f8525/8621 devices that allows the controller to access external memory devices (such as flash, eprom, sram, etc.) as program or data memory. the physical implementation of the interface uses 27 pins. these pins are reserved for external address/ data bus functions; they are multiplexed with i/o port pins on four ports. three i/o ports are multiplexed with the address/data bus, while the fourth port is multiplexed with the bus control signals. the i/o port functions are enabled when the ebdis bit in the memcon register is set (see register 6-1). a list of the multiplexed pins and their functions is provided in table 6-1. as implemented in the pic18f8525/8621 devices, the interface operates in a similar manner to the external memory interface introduced on pic18c601/801 micro- controllers. the most notable difference is that the interface on pic18f8525/8621 devices only operates in 16-bit modes. the 8-bit mode is not supported. for a more complete discussion of the operating modes that use the external memory interface, refer to section 4.1.1 ?PIC18F6525/6621/8525/8621 program memory modes? . 6.1 program memory modes and the external memory interface as previously noted, pic18f8525/8621 controllers are capable of operating in any one of four program mem- ory modes using combinations of on-chip and external program memory. the functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the ebdis bit. in microprocessor mode , the external bus is always active and the port pins have only the external bus function. in microcontroller mode, the bus is not active and the pins have their port functions only. writes to the memcom register are not permitted. in microprocessor with boot block or extended microcontroller mode, the external program memory bus shares i/o port functions on the pins. when the device is fetching or doing table read/table write oper- ations on the external program memory space, the pins will have the external bus function. if the device is fetching and accessing internal program memory loca- tions only, the ebdis control bit will change the pins from external memory to i/o port functions. when ebdis = 0 , the pins function as the external bus. when ebdis = 1 , the pins function as i/o ports. register 6-1: memcon: memory control register note: the external memory interface is not implemented on PIC18F6525/6621 (64-pin) devices. r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis ?wait1wait0 ? ?wm1wm0 bit 7 bit 0 bit 7 ebdis : external bus disable bit 1 = external system bus disabled, all external bus drivers are mapped as i/o ports 0 = external system bus enabled and i/o ports are disabled bit 6 unimplemented : read as ? 0 ? bit 5-4 wait1:wait0 : table reads and writes bus cycle wait count bits 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented : read as ? 0 ? bit 1-0 wm1:wm0 : tblwrt operation with 16-bit bus bits 1x = word write mode: tablat<0> and tablat<1> word output, wrh active when tablat<1> written 01 = byte select mode: tablat data copied on both msb and lsb, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both msb and lsb, wrh or wrl will activate note: the memcon register is unimplemented and reads all ? 0 ?s when the device is in microcontroller mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 72 ? 2005 microchip technology inc. if the device fetches or accesses external memory while ebdis = 1 , the pins will switch to external bus. if the ebdis bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. at that time, the pins will change from external bus to i/o ports. when the device is executing out of internal memory (ebdis = 0 ) in microprocessor with boot block mode or extended microcontroller mode, the control signals will not be active. they will go to a state where the ad<15:0> and a<19:16> are tri-state; the ce , oe , wrh , wrl , ub and lb signals are ? 1 ? and ale and ba0 are ? 0 ?. table 6-1: pic18f8525/8621 external bus ? i/o port functions name port bit function rd0/ad0 portd bit 0 input/output or system bus address bit 0 or data bit 0 rd1/ad1 portd bit 1 input/output or system bus address bit 1 or data bit 1 rd2/ad2 portd bit 2 input/output or system bus address bit 2 or data bit 2 rd3/ad3 portd bit 3 input/output or system bus address bit 3 or data bit 3 rd4/ad4 portd bit 4 input/output or system bus address bit 4 or data bit 4 rd5/ad5 portd bit 5 input/output or system bus address bit 5 or data bit 5 rd6/ad6 portd bit 6 input/output or system bus address bit 6 or data bit 6 rd7/ad7 portd bit 7 input/output or system bus address bit 7 or data bit 7 re0/ad8 porte bit 0 input/output or system bus address bit 8 or data bit 8 re1/ad9 porte bit 1 input/output or system bus address bit 9 or data bit 9 re2/ad10 porte bit 2 input/output or system bus address bit 10 or data bit 10 re3/ad11 porte bit 3 input/output or system bus address bit 11 or data bit 11 re4/ad12 porte bit 4 input/output or system bus address bit 12 or data bit 12 re5/ad13 porte bit 5 input/output or system bus address bit 13 or data bit 13 re6/ad14 porte bit 6 input/output or system bus address bit 14 or data bit 14 re7/ad15 porte bit 7 input/output or system bus address bit 15 or data bit 15 rh0/a16 porth bit 0 input/output or system bus address bit 16 rh1/a17 porth bit 1 input/output or system bus address bit 17 rh2/a18 porth bit 2 input/output or system bus address bit 18 rh3/a19 porth bit 3 input/output or system bus address bit 19 rj0/ale portj bit 0 input/output or system bus address latch enable (ale) control pin rj1/oe portj bit 1 input/output or system bus output enable (oe ) control pin rj2/wrl portj bit 2 input/output or system bus write low (wrl ) control pin rj3/wrh portj bit 3 input/output or system bus write high (wrh ) control pin rj4/ba0 portj bit 4 input/output or system bus byte address bit 0 rj5/ce portj bit 5 input/output or system bus chip enable (ce ) control pin rj6/lb portj bit 6 input/output or system bus lower byte enable (lb ) control pin rj7/ub portj bit 7 input/output or system bus upper byte enable (ub ) control pin
? 2005 microchip technology inc. ds39612b-page 73 PIC18F6525/6621/8525/8621 6.2 16-bit mode the external memory interface implemented in pic18f8525/8621 devices operates only in 16-bit mode. the mode selection is not software configurable but is programmed via the configuration bits. the wm1:wm0 bits in the memcon register determine three types of connections in 16-bit mode. they are referred to as: 16-bit byte write 16-bit word write 16-bit byte select these three different configurations allow the designer maximum flexibility in using 8-bit and 16-bit memory devices. for all 16-bit modes, the address latch enable (ale) pin indicates that the address bits, a15:a0, are available on the external memory interface bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in sleep mode. in byte select mode, jedec standard flash memories will require ba0 for the byte address line and one i/o line, to select between byte and word mode. the other 16-bit modes do not need ba0. jedec standard static ram memories will use the ub or lb signals for byte selection. 6.2.1 16-bit byte write mode figure 6-1 shows an example of 16-bit byte write mode for pic18f8525/8621 devices. this mode is used for two separate 8-bit memories connected for 16-bit operation. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate wrh or wrl control line is strobed on the lsb of the tblptr. figure 6-1: 16-bit byte write mode example ad<7:0> a<19:16> ale d<15:8> 373 a d<7:0> a<19:0> a d<7:0> 373 oe wrh oe oe wr (1) wr (1) ce ce note 1: this signal only applies to table writes. see section 5.1 ?table reads and table writes? . wrl d<7:0> (lsb) (msb) pic18f8x2x d<7:0> ad<15:8> address bus data bus control lines ce
PIC18F6525/6621/8525/8621 ds39612b-page 74 ? 2005 microchip technology inc. 6.2.2 16-bit word write mode figure 6-2 shows an example of 16-bit word write mode for pic18f8525/8621 devices. this mode is used for word-wide memories which include some of the eprom and flash type memories. this mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word- wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address (tblptr<0> = 0 ), the tablat data is transferred to a holding latch and the external address data bus is tri- stated for the data portion of the bus cycle. no write signals are activated. during a tblwt cycle to an odd address (tblptr<0> = 1 ), the tablat data is presented on the upper byte of the ad15:ad0 bus. the contents of the holding latch are presented on the lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is unused. the signal on the ba0 pin indicates the lsb of the tblptr but it is left unconnected. instead, the ub and lb signals are active to select both bytes. the obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. figure 6-2: 16-bit word write mode example ad<7:0> pic18f8x2x ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> a d<15:0> oe wr (1) ce d<15:0> jedec word eprom memory address bus data bus control lines note 1: this signal only applies to table writes. see section 5.1 ?table reads and table writes? . ce
? 2005 microchip technology inc. ds39612b-page 75 PIC18F6525/6621/8525/8621 6.2.3 16-bit byte select mode figure 6-3 shows an example of 16-bit byte select mode for pic18f8525/8621 devices. this mode allows table write operations to word-wide external memories with byte selection capability. this generally includes both word-wide flash and sram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is not used. the ba0 or ub /lb signals are used to select the byte to be written based on the least significant bit of the tblptr register. flash and sram devices use different control signal combinations to implement byte select mode. jedec standard flash memories require that a controller i/o port pin be connected to the memory?s byte/word pin to provide the select signal. they also use the ba0 signal from the controller as a byte address. jedec standard static ram memories, on the other hand, use the ub or lb signals to select the byte. figure 6-3: 16-bit byte select mode example ad<7:0> pic18f8x2x ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> wrl ba0 jedec word a d<15:0> a<20:1> ce d<15:0> i/o oe wr (1) a0 byte/word flash memory jedec word a d<15:0> ce d<15:0> oe wr (1) lb ub sram memory lb ub 138 (2) address bus data bus control lines note 1: this signal only applies to table writes. see section 5.1 ?table reads and table writes? . 2: demultiplexing is only required when multiple memory devices are accessed.
PIC18F6525/6621/8525/8621 ds39612b-page 76 ? 2005 microchip technology inc. 6.2.4 16-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 6-4 through figure 6-6. figure 6-4: external memory bus timi ng for tblrd (microprocessor mode) figure 6-5: external memo ry bus timing for tblrd (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 ale oe 3aabh wrh wrl ad<15:0> ba0 cf33h from 007556h 9256h 0e55h ? 1 ? ? 1 ? ? 1 ? ? 1 ? table read of 92h from 199e67h 1 t cy wait q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q a<19:16> ce ? 0 ? ? 0 ? memory cycle instruction execution tblrd cycle 1 tblrd cycle 2 00h 0ch opcode fetch movlw 55h q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<15:0> ce opcode fetch opcode fetch opcode fetch tblrd* tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch cf33h tblrd 92h from 199e67h 9256h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw
? 2005 microchip technology inc. ds39612b-page 77 PIC18F6525/6621/8525/8621 figure 6-6: external memory bus timing for sleep (microprocessor mode) q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah ad<15:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 0003h 3aabh 0e55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h
PIC18F6525/6621/8525/8621 ds39612b-page 78 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 79 PIC18F6525/6621/8525/8621 7.0 data eeprom memory the data eeprom is readable and writable during normal operation over the entire v dd range. the data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfr). there are five sfrs used to read and write the program and data eeprom memory. these registers are: eecon1 eecon2 eedata eeadrh eeadr the eeprom data memory allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write. eeadr and eeadrh hold the address of the eeprom location being accessed. these devices have 1024 bytes of data eeprom with an address range from 00h to 3ffh. the eeprom data memory is rated for high erase/ write cycles. a byte write automatically erases the loca- tion and writes the new data (erase-before-write). the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip-to-chip. please refer to parameter d122 ( section 27.0 ?electrical characteristics? ) for exact limits. 7.1 eeadr and eeadrh the address register pair can address up to a maximum of 1024 bytes of data eeprom. the two most significant bits of the address are stored in eeadrh, while the remaining eight least significant bits are stored in eeadr. the six most significant bits of eeadrh are unused and are read as ? 0 ?. 7.2 eecon1 and eecon2 registers eecon1 is the control register for eeprom memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the eeprom write sequence. control bits rd and wr initiate read and write operations, respectively. these bits cannot be cleared, only set in software. they are cleared in hardware at the completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal operation. in these situations, the user can check the wrerr bit and rewrite the location. it is necessary to reload the data and address registers (eedata and eeadr) due to the reset condition forcing the contents of the registers to zero. note: during normal operation, the wrerr bit is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. note: interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software.
PIC18F6525/6621/8525/8621 ds39612b-page 80 ? 2005 microchip technology inc. register 7-1: eecon1 register (address fa6h) r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program/data eeprom memory select bit 1 = access flash program memory 0 = access data eeprom memory bit 6 cfgs: flash program/data eeprom or configuration select bit 1 = access configuration or calibration registers 0 = access flash program or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: flash program/data eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr or any wdt reset during self-timed programming in normal operation) 0 = the write operation completed note: when a wrerr occurs, the eepgd or free bits are not cleared. this allows tracing of the error condition. bit 2 wren: flash program/data eeprom write enable bit 1 = allows write cycles to flash program/data eeprom 0 = inhibits write cycles to flash program/data eeprom bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = does not initiate an eeprom read legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 81 PIC18F6525/6621/8525/8621 7.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadrh:eeadr register pair, clear the eepgd control bit (eecon1<7>), clear the cfgs control bit (eecon1<6>) and then set the rd control bit (eecon1<0>). the data is available for the very next instruction cycle; therefore, the eedata register can be read by the next instruction. eedata will hold this value until another read operation or until it is written to by the user (during a write operation). example 7-1: data eeprom read 7.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadrh:eeadr register pair and the data written to the eedata register. then the sequence in example 7-2 must be followed to initiate the write cycle. the write will not initiate if the above sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code execution (i.e., runaway programs). the wren bit should be kept clear at all times except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, eecon1, eeadrh, eeadr and eedata cannot be modified. the wr bit will be inhibited from being set unless the wren bit is set. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom write complete interrupt flag bit (eeif) is set. the user may either enable this interrupt or poll this bit. eeif must be cleared by software. example 7-2: data eeprom write movlw data_ee_addrh ; movwf eeadrh ; upper bits of data memory address to read movlw data_ee_addr ; movwf eeadr ; lower bits of data memory address to read bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, rd ; eeprom read movf eedata, w ; w = eedata movlw data_ee_addrh ; movwf eeadrh ; upper bits of data memory address to write movlw data_ee_addr ; movwf eeadr ; lower bits of data memory address to write movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, eepgd ; point to data memory bcf eecon1, cfgs ; access eeprom bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 0x55 ; required movwf eecon2 ; write 55h sequence movlw 0xaa ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts ; user code execution bcf eecon1, wren ; disable writes on write complete (eeif set)
PIC18F6525/6621/8525/8621 ds39612b-page 82 ? 2005 microchip technology inc. 7.5 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 7.6 protection against spurious write there are conditions when the user may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 7.7 operation during code-protect data eeprom memory has its own code-protect mechanism. external read and write operations are disabled if either of these mechanisms are enabled. refer to section 24.0 ?special features of the cpu? , for additional information. 7.8 using the data eeprom the data eeprom is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). frequently changing values will typically be updated more often than specification d124. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 7-3. example 7-3: data eeprom refresh routine clrf eeadr ; start at address 0 clrf eeadrh ; bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again incfsz eeadrh, f ; increment the high address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts
? 2005 microchip technology inc. ds39612b-page 83 PIC18F6525/6621/8525/8621 table 7-1: registers associated with data eeprom memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u eeadrh ? ? ? ? ? ? ee addr register high ---- --00 ---- --00 eeadr data eeprom address register 0000 0000 0000 0000 eedata data eeprom data register 0000 0000 0000 0000 eecon2 data eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 ? cmip ?eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 -1-1 1111 pir2 ? cmif ?eeif bclif lvdif tmr3if ccp2if -0-0 0000 ---0 0000 pie2 ? cmie ?eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 ---0 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access.
PIC18F6525/6621/8525/8621 ds39612b-page 84 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 85 PIC18F6525/6621/8525/8621 8.0 8 x 8 hardware multiplier 8.1 introduction an 8 x 8 hardware multiplier is included in the alu of the PIC18F6525/6621/8525/8621 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored in the 16-bit product register pair (prodh:prodl). the multiplier does not affect any flags in the alusta register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 8-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. 8.2 operation example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiply. to account for the signed bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine table 8-1: performance comparison movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w ; btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s27.6 s 69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s36.4 s 91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s96.8 s 242 s hardware multiply 24 24 2.4 s9.6 s 24 s 16 x 16 signed without hardware multiply 52 254 25.4 s 102.6 s 254 s hardware multiply 36 36 3.6 s14.4 s 36 s
PIC18F6525/6621/8525/8621 ds39612b-page 86 ? 2005 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers, res3:res0. equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the signed bits of the arguments, each argument pairs? most significant bit (msb) is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l,w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 )
? 2005 microchip technology inc. ds39612b-page 87 PIC18F6525/6621/8525/8621 9.0 interrupts the PIC18F6525/6621/8525/8621 devices have multi- ple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. the high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. high priority interrupt events will override any low priority interrupts that may be in progress. there are thirteen registers which are used to control interrupt operation. they are: rcon intcon intcon2 intcon3 pir1, pir2, pir3 pie1, pie2, pie3 ipr1, ipr2, ipr3 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its operation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set. setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit which enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used) which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit.
PIC18F6525/6621/8525/8621 ds39612b-page 88 ? 2005 microchip technology inc. figure 9-1: interrupt logic tmr0ie gieh/gie giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel/peie interrupt to cpu vector to location ipen ipen 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit tmr1if tmr1ie tmr1ip xxxxif xxxxie xxxxip additional peripheral interrupts tmr1if tmr1ie tmr1ip high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts gie/geih
? 2005 microchip technology inc. ds39612b-page 89 PIC18F6525/6621/8525/8621 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. register 9-1: intcon: interrupt control register note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen (rcon<7>) = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen (rcon<7>) = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen (rcon<7>) = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen (rcon<7>) = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 90 ? 2005 microchip technology inc. register 9-2: intcon2: interrupt control regi ster 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 i ntedg3 tmr0ip int3ip rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 : external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1 : external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2 : external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3 : external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 = high priority 0 = low priority bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 2005 microchip technology inc. ds39612b-page 91 PIC18F6525/6621/8525/8621 register 9-3: intcon3: interrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
PIC18F6525/6621/8525/8621 ds39612b-page 92 ? 2005 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request flag registers (pir1, pir2 and pir3). register 9-4: pir1: peripheral interrupt request (flag) register 1 note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit (1) 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred note 1: enabled only in microcontroller mode for pic18f8525/8621 devices. bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if : usart1 receive interrupt flag bit 1 = the usart1 receive buffer, rcregx, is full (cleared when rcregx is read) 0 = the usart1 receive buffer is empty bit 4 tx1if : usart1 transmit interrupt flag bit 1 = the usart1 transmit buffer, txregx, is empty (cleared when txregx is written) 0 = the usart1 transmit buffer is full bit 3 sspif : master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : eccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 93 PIC18F6525/6621/8525/8621 register 9-5: pir2: peripheral interrupt request (flag) register 2 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?cmif ? eeif bclif lvdif tmr3if ccp2if bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmif : comparator interrupt flag bit 1 = the comparator input has changed (must be cleared in software) 0 = the comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif : data eeprom/flash write operation interrupt flag bit 1 = the write operation is complete (must be cleared in software) 0 = the write operation is not complete, or has not been started bit 3 bclif : bus collision interrupt flag bit 1 = a bus collision occurred while the mssp module (configured in i 2 c master mode) was transmitting (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif : low-voltage detect interrupt flag bit 1 = a low voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if : tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if : eccp2 interrupt flag bit capture mode: 1 = a tmr1 or tmr3 register capture occurred (must be cleared in software) 0 = no tmr1 or tmr3 register capture occurred compare mode: 1 = a tmr1 or tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1 or tmr3 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 94 ? 2005 microchip technology inc. register 9-6: pir3: peripheral interrupt request (flag) register 3 u-0 u-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2if : usart2 receive interrupt flag bit 1 = the usart2 receive buffer, rcregx, is full (cleared when rcregx is read) 0 = the usart2 receive buffer is empty bit 4 tx2if : usart2 transmit interrupt flag bit 1 = the usart2 transmit buffer, txregx, is empty (cleared when txregx is written) 0 = the usart2 transmit buffer is full bit 3 tmr4if : tmr3 overflow interrupt flag bit 1 = tmr4 register overflowed (must be cleared in software) 0 = tmr4 register did not overflow bit 2-0 ccpxif : ccpx interrupt flag bit (eccp3, ccp4 and ccp5) capture mode: 1 = a tmr1 or tmr3 register capture occurred (must be cleared in software) 0 = no tmr1 or tmr3 register capture occurred compare mode: 1 = a tmr1 or tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1 or tmr3 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 95 PIC18F6525/6621/8525/8621 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2 and pie3). when the ipen bit (rcon<7>) is ? 0 ?, the peie bit must be set to enable any of these peripheral interrupts. register 9-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit (1) 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt note: enabled only in microcontroller mode for pic18f8525/8621 devices. bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rc1ie : usart1 receive interrupt enable bit 1 = enables the usart1 receive interrupt 0 = disables the usart1 receive interrupt bit 4 tx1ie : usart1 transmit interrupt enable bit 1 = enables the usart1 transmit interrupt 0 = disables the usart1 transmit interrupt bit 3 sspie : master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie : eccp1 interrupt enable bit 1 = enables the eccp1 interrupt 0 = disables the eccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 96 ? 2005 microchip technology inc. register 9-8: pie2: peripheral interrupt enable register 2 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ?cmie ? eeie bclie lvdie tmr3ie ccp2ie bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmie : comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disables the comparator interrupt bit 5 unimplemented: read as ? 0 ? bit 4 eeie : data eeprom/flash write operation interrupt enable bit 1 = enables the write operation interrupt 0 = disables the write operation interrupt bit 3 bclie : bus collision interrupt enable bit 1 = enables the bus collision interrupt 0 = disables the bus collision interrupt bit 2 lvdie : low-voltage detect interrupt enable bit 1 = enables the low-voltage detect interrupt 0 = disables the low-voltage detect interrupt bit 1 tmr3ie : tmr3 overflow interrupt enable bit 1 = enables the tmr3 overflow interrupt 0 = disables the tmr3 overflow interrupt bit 0 ccp2ie : eccp2 interrupt enable bit 1 = enables the eccp2 interrupt 0 = disables the eccp2 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 97 PIC18F6525/6621/8525/8621 register 9-9: pie3: peripheral interrupt enable register 3 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ie : usart2 receive interrupt enable bit 1 = enables the usart2 receive interrupt 0 = disables the usart2 receive interrupt bit 4 tx2ie : usart2 transmit interrupt enable bit 1 = enables the usart2 transmit interrupt 0 = disables the usart2 transmit interrupt bit 3 tmr4ie : tmr4 to pr4 match interrupt enable bit 1 = enables the tmr4 to pr4 match interrupt 0 = disables the tmr4 to pr4 match interrupt bit 2-0 ccpxie : ccpx interrupt enable bit (eccp3, ccp4 and ccp5) 1 = enables the ccpx interrupt 0 = disables the ccpx interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 98 ? 2005 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2 and ipr3). the operation of the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip: parallel slave port read/write interrupt priority bit (1) 1 =high priority 0 = low priority note: enabled only in microcontroller mode for pic18f8525/8621 devices. bit 6 adip : a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rc1ip : usart1 receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx1ip : usart1 transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip : master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 ccp1ip : eccp1 interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr2ip : tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip : tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 99 PIC18F6525/6621/8525/8621 register 9-11: ipr2: peripheral interrupt priority register 2 u-0 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ?cmip ? eeip bclip lvdip tmr3ip ccp2ip bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 cmip : comparator interrupt priority bit 1 =high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 eeip : data eeprom/flash write operation interrupt priority bit 1 =high priority 0 = low priority bit 3 bclip : bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 lvdip : low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip : tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 ccp2ip : eccp2 interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 100 ? 2005 microchip technology inc. register 9-12: ipr3: peripheral interrupt priority register 3 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ip : usart2 receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx2ip : usart2 transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 tmr4ip : tmr4 to pr4 match interrupt priority bit 1 =high priority 0 = low priority bit 2-0 ccpxip : ccpx interrupt priority bit (eccp3, ccp4 and ccp5) 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 101 PIC18F6525/6621/8525/8621 9.5 rcon register the rcon register contains the ipen bit which is used to enable prioritized interrupts. the functions of the other bits in this register are discussed in more detail in section 4.14 ?rcon register? . register 9-13: rcon: reset control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16 compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-4. bit 3 to : watchdog time-out flag bit for details of bit operation, see register 4-4. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-4. bit 1 por : power-on reset status bit for details of bit operation, see register 4-4. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-4. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 102 ? 2005 microchip technology inc. 9.6 int0 interrupt external interrupts on the rb0/int0/flt0, rb1/int1, rb2/int2 and rb3/int3 pins are edge-triggered; either rising if the corresponding intedgx bit is set in the intcon2 register, or falling if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxf, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxe. flag bit, intxf, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from sleep if bit intxie was set prior to going into sleep. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. the interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits: int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0; it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh 00h) will set flag bit tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l registers (ffffh 0000h) will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3 ?fast register stack? ), the user may need to save the wreg, status and bsr registers in software. depending on the user?s application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
? 2005 microchip technology inc. ds39612b-page 103 PIC18F6525/6621/8525/8621 10.0 i/o ports depending on the device selected, there are either seven or nine i/o ports available on PIC18F6525/6621/ 8525/8621 devices. some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch register) the data latch (lat) register is useful for read-modify- write operations on the value that the i/o pins are driving. a simplified version of a generic i/o port and its operation is shown in figure 10-1. figure 10-1: simplified block diagram of port/lat/ tris operation 10.1 porta, trisa and lata registers porta is a 7-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register, read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/ t0cki pin is a schmitt trigger input and an open-drain output. all other ra port pins have ttl input levels and full cmos output drivers. the ra6 pin is only enabled as a general i/o pin in ecio and rcio oscillator modes. the other porta pins are multiplexed with analog inputs and the analog v ref + and v ref - inputs. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register 1). the trisa register controls the direction of the ra pins even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 10-1: initializing porta q d ck wr lat + data latch i/o pin rd port wr port tris rd lat data bus note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra6 and ra4 are configured as digital inputs. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 0x0f ; configure a/d movwf adcon1 ; for digital inputs movlw 0x0f ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<6:4> as outputs
PIC18F6525/6621/8525/8621 ds39612b-page 104 ? 2005 microchip technology inc. figure 10-2: block diagram of ra3:ra0 and ra5 pins figure 10-3: block diagram of ra4/t0cki pin figure 10-4: block diagram of ra6 pin (when enabled as i/o) data bus q d q ck q d q ck qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or porta data bus wr trisa rd porta data latch tris latch schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en rd lata wr lata or porta note 1: i/o pins have protection diodes to v dd and v ss . rd trisa data bus q d q ck qd en p n wr lata wr data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata ecra6 or ttl input buffer ecra6 or rcra6 enable rcra6 enable trisa q d q ck trisa
? 2005 microchip technology inc. ds39612b-page 105 PIC18F6525/6621/8525/8621 table 10-1: porta functions table 10-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/v ref - bit 2 ttl input/output, analog input or v ref -. ra3/an3/v ref + bit 3 ttl input/output, analog input or v ref +. ra4/t0cki bit 4 st input/output or external clock input for timer0. output is open-drain type. ra5/an4/lvdin bit 5 ttl input/output, analog input or low-voltage detect input. osc2/clko/ra6 bit 6 ttl osc2, clock output or i/o pin legend: ttl = ttl input, st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ?ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 -x0x 0000 -u0u 0000 lata ?lata6 (1) lata data output register -xxx xxxx -uuu uuuu trisa ?trisa6 (1) porta data direction register -111 1111 -111 1111 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: ra6 and associated bits are configured as port pins in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes.
PIC18F6525/6621/8525/8621 ds39612b-page 106 ? 2005 microchip technology inc. 10.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register, read and write the latched output value for portb. example 10-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb3:rb0) are the external interrupt pins, int3 through int0. in order to use these pins as external interrupts, the corresponding trisb bit must be set to ? 1 ?. the other four portb pins (rb7:rb4) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). b) clear flag bit rbif. a mismatch condition will continue to set flag bit, rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. for pic18f8525/8621 devices, rb3 can be configured by the configuration bit, ccp2mx, as the alternate peripheral pin for the eccp2 module. this is only available when the device is configured in microprocessor, microprocessor with boot block or extended microcontroller operating modes. the rb5 pin is used as the lvp programming pin. when the lvp configuration bit is programmed, this pin loses the i/o function and becomes a programming test function. figure 10-5: block diagram of rb7:rb4 pins note: on a power-on reset, these pins are configured as digital inputs. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs note: when lvp is enabled, the weak pull-up on rb5 is disabled. data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer st buffer rb7:rb5 in serial programming mode q3 q1 rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>).
? 2005 microchip technology inc. ds39612b-page 107 PIC18F6525/6621/8525/8621 figure 10-6: block diagram of rb2:rb0 pins figure 10-7: block diagram of rb3 pin data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr trisb rd trisb rd portb weak pull-up rd port intx i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropria te tris bit(s) and clear the rbpu bit (intcon2<7>). wr latb or wr portb data latch p v dd q d ck q d en data bus wr latb or wr trisb rd trisb rd portb weak pull-up eccp2 or int3 ttl input buffer schmitt trigger buffer tris latch rd latb wr portb rbpu (2) ck d enable (3) eccp output rd portb eccp output (3) 1 0 p n v dd v ss i/o pin (1) q ccp2mx ccp2mx = 0 note 1: i/o pin has diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropr iate tris bit(s) and clear the rbpu bit (intcon2<7>). 3: for pic18f8525/8621 parts, the eccp2 input/output is multiplexed with rb3 if the ccp2mx bit is enabled (= 0 ) in the configuration register and the device is operating in microprocessor, microprocessor with boot block or extended microcontroller mode.
PIC18F6525/6621/8525/8621 ds39612b-page 108 ? 2005 microchip technology inc. table 10-3: portb functions table 10-4: summary of registers associated with portb name bit# buffer function rb0/int0/flt0 bit 0 ttl/st (1) input/output pin or external interrupt input 0, eccp1 pwm fault input. internal software programmable weak pull-up. rb1/int1 bit 1 ttl/st (1) input/output pin or external interrupt input 1. internal software programmable weak pull-up. rb2/int2 bit 2 ttl/st (1) input/output pin or external interrupt input 2. internal software programmable weak pull-up. rb3/int3/ eccp2 (3) /p2a (3) bit 3 ttl/st (4) input/output pin, external interrupt input 3, enhanced capture 2 input/ compare 2 output/pwm 2 output or enhanced pwm output p2a. internal software programmable weak pull-up. rb4/kbi0 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5/kbi1/pgm bit 5 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. low-voltage icsp? enable pin. rb6/kbi2/pgc bit 6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7/kbi3/pgd bit 7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: valid for pic18f8525/8621 devices in all operating modes except microcontroller mode when ccp2mx is not set. rc1 is the default assignment for eccp2/pa2 when ccp2mx is set in all devices; re7 is the alternate assignment for pic18f8525/8621 devices in microcontroller mode when ccp2mx is clear. 4: this buffer is a schmitt trigger input when configured as the eccp2 input. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu latb latb data output register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 1111 1111 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 1100 0000 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 2005 microchip technology inc. ds39612b-page 109 PIC18F6525/6621/8525/8621 10.3 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register, read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 10-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. rc1 is normally configured by configuration bit, ccp2mx, as the default peripheral pin of the eccp2 module (default/erased state, ccp2mx = 1 ). example 10-3: initializing portc figure 10-8: portc block diagram (peripheral output override) note: on a power-on reset, these pins are configured as digital inputs. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs portc/peripheral out select data bus wr latc wr trisc data latch tris latch rd trisc q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd portc peripheral data in i/o pin (1) or wr portc rd latc schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . 2: peripheral output enable is only active if peripheral select is active. tris override peripheral output logic tris override pin override peripheral rc0 yes timer1 oscillator for timer1/timer3 rc1 yes timer1 osc for timer1/timer3, eccp2 i/o rc2 yes eccp1 i/o rc3 yes spi?/i 2 c? master clock rc4 yes i 2 c data out rc5 yes spi data out rc6 yes usart1 async xmit, sync clock rc7 yes usart1 sync data out enable (2)
PIC18F6525/6621/8525/8621 ds39612b-page 110 ? 2005 microchip technology inc. table 10-5: portc functions table 10-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t13cki bit 0 st input/output port pin, timer1 oscillator output or timer1/timer3 clock input. rc1/t1osi/ eccp2 (1) /p2a (1) bit 1 st input/output port pin, timer1 oscillator input, enhanced capture 2 input/compare 2 output/pwm 2 output or enhanced pwm output p2a. rc2/eccp1/p1a bit 2 st input/output port pin, enhanced capture 1 input/compare 1 output/ pwm 1 output or enhanced pwm output p1a. rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi? and i 2 c? modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx1/ck1 bit 6 st input/output port pin, addressable usart1 asynchronous transmit or addressable usart1 synchronous clock. rc7/rx1/dt1 bit 7 st input/output port pin, addressable usart1 asynchronous receive or addressable usart1 synchronous data. legend: st = schmitt trigger input note 1: valid when ccp2mx is set in all devices and in all operating modes (default). re7 is the alternate assignment for eccp2/p2a for all PIC18F6525/6621 devices and pic18f8525/8621 devices in microcontroller modes when ccp2mx is not set; rb3 is the alternate assignment for pic18f8525/8621 devices in all other operating modes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data output register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
? 2005 microchip technology inc. ds39612b-page 111 PIC18F6525/6621/8525/8621 10.4 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register, read and write the latched output value for portd. portd is an 8-bit port with schmitt trigger input buffers. each pin is individually configurable as an input or output. portd is multiplexed with the system bus as the external memory interface. i/o port functions are only available when the system bus is disabled by setting the ebdis bit in the memcom register (memcon<7>). when operating as the external memory interface, portd is the low-order byte of the multiplexed address/data bus (ad7:ad0). portd can also be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. see section 10.10 ?parallel slave port? for additional information on the parallel slave port (psp). example 10-4: initializing portd figure 10-9: port d block diagram in i/o port mode note: on a power-on reset, these pins are configured as digital inputs. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs data bus wr latd wr trisd rd portd data latch tris latch rd trisd schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd latd or portd note 1: i/o pins have diode protection to v dd and v ss .
PIC18F6525/6621/8525/8621 ds39612b-page 112 ? 2005 microchip technology inc. figure 10-10: portd block diagram in system bus mode instruction register bus enable data/tris out drive bus system bus control data bus wr latd wr trisd rd portd data latch tris latch rd trisd ttl input buffer i/o pin (1) q d ck q d ck en qd en rd latd or portd 0 1 port data instruction read note 1: i/o pins have protection diodes to v dd and v ss .
? 2005 microchip technology inc. ds39612b-page 113 PIC18F6525/6621/8525/8621 table 10-7: portd functions table 10-8: summary of registers associated with portd name bit# buffer type function rd0/ad0 (2) /psp0 bit 0 st/ttl (1) input/output port pin, address/data bus bit 0 or parallel slave port bit 0. rd1/ad1 (2) /psp1 bit 1 st/ttl (1) input/output port pin, address/data bus bit 1 or parallel slave port bit 1. rd2/ad2 (2) /psp2 bit 2 st/ttl (1) input/output port pin, address/data bus bit 2 or parallel slave port bit 2. rd3/ad3 (2) /psp3 bit 3 st/ttl (1) input/output port pin, address/data bus bit 3 or parallel slave port bit 3. rd4/ad4 (2) /psp4 bit 4 st/ttl (1) input/output port pin, address/data bus bit 4 or parallel slave port bit 4. rd5/ad5 (2) /psp5 bit 5 st/ttl (1) input/output port pin, address/data bus bit 5 or parallel slave port bit 5. rd6/ad6 (2) /psp6 bit 6 st/ttl (1) input/output port pin, address/data bus bit 6 or parallel slave port bit 6. rd7/ad7 (2) /psp7 bit 7 st/ttl (1) input/output port pin, address/data bus bit 7 or parallel slave port bit 7. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in system bus or parallel slave port mode. 2: external memory interface functions are only available on pic18f8525/8621 devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data output register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 pspcon (1) ibf obf ibov pspmode ? ? ? ? 0000 ---- 0000 ---- memcon (2) ebdis ? wait1 wait0 ? ? wm1 wm0 0-00 --00 0-00 --00 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by portd. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices. 2: this register is unused on PIC18F6525/6621 devices and reads as ? 0 ?.
PIC18F6525/6621/8525/8621 ds39612b-page 114 ? 2005 microchip technology inc. 10.5 porte, trise and late registers porte is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the late register, read and write the latched output value for porte. porte is an 8-bit port with schmitt trigger input buffers. each pin is individually configurable as an input or output. porte is multiplexed with the eccp module (table 10-9). on pic18f8525/8621 devices, porte is also multiplexed with the system bus as the external memory interface; the i/o bus is available only when the system bus is disabled by setting the ebdis bit in the memcon register (memcon<7>). if the device is configured in microprocessor or extended microcontroller mode, then the porte<7:0> becomes the high byte of the address/ data bus for the external program memory interface. in microcontroller mode, the porte<2:0> pins become the control inputs for the parallel slave port when bit pspmode (pspcon<4>) is set. (refer to section 4.1.1 ?PIC18F6525/6621/8525/8621 program memory modes? for more information.) when the parallel slave port is active, three porte pins (re0/ad8/rd /p2d, re1/ad9/wr /p2c and re2/ ad10/cs /p2b) function as its control inputs. this automatically occurs when the pspmode bit (pspcon<4>) is set. users must also make certain that bits trise<2:0> are set to configure the pins as digital inputs and the adcon1 register is configured for digital i/o. the porte psp control functions are summarized in table 10-9. pin re7 can be configured as the alternate peripheral pin for the eccp2 module when the device is operating in microcontroller mode. this is done by clearing the configuration bit, ccp2mx, in the config3h configuration register (config3h<0>). example 10-5: initializing porte note: for pic18f8525/8621 (80-pin) devices operating in extended microcontroller mode, porte defaults to the system bus on power-on reset. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 0x03 ; value used to ; initialize data ; direction movwf trise ; set re1:re0 as inputs ; re7:re2 as outputs
? 2005 microchip technology inc. ds39612b-page 115 PIC18F6525/6621/8525/8621 figure 10-11: porte block diagram in i/o mode figure 10-12: porte block diagram in system bus mode peripheral out select data bus wr late wr trise data latch tris latch rd trise q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd porte peripheral data in i/o pin (1) or wr porte rd late schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override peripheral enable tris override pin override peripheral re0 yes external bus re1 yes external bus re2 yes external bus re3 yes external bus re4 yes external bus re5 yes external bus re6 yes external bus re7 yes external bus instruction register bus enable data/tris out drive bus system bus control data bus wr late wr trise rd porte data latch tris latch rd trise ttl input buffer i/o pin (1) q d ck q d ck en qd en rd late or porte 0 1 port data instruction read note 1: i/o pins have protection diodes to v dd and v ss .
PIC18F6525/6621/8525/8621 ds39612b-page 116 ? 2005 microchip technology inc. table 10-9: porte functions table 10-10: summary of registers associated with porte name bit# buffer type function re0/ad8/rd /p2d bit 0 st/ttl (1) input/output port pin, address/data bit 8, read control for parallel slave port or enhanced pwm 2 output p2d for rd (psp control mode): 1 = not a read operation 0 = read operation, reads portd register (if chip selected) re1/ad9/wr /p2c bit 1 st/ttl (1) input/output port pin, address/data bit 9, write control for parallel slave port or enhanced pwm 2 output p2c for wr (psp control mode): 1 = not a write operation 0 = write operation, writes portd register (if chip selected) re2/ad10/cs /p2b bit 2 st/ttl (1) input/output port pin, address/data bit 10, chip select control for parallel slave port or enhanced pwm 2 output p2b for cs (psp control mode): 1 = device is not selected 0 = device is selected re3/ad11/p3c (2) bit 3 st/ttl (1) input/output port pin, address/data bit 11 or enhanced pwm 3 output p3c. re4/ad12/p3b (2) bit 4 st/ttl (1) input/output port pin, address/data bit 12 or enhanced pwm 3 output p3b. re5/ad13/p1c (2) bit 5 st/ttl (1) input/output port pin, address/data bit 13 or enhanced pwm 1 output p1c. re6/ad14/p1b (2) bit 6 st/ttl (1) input/output port pin, address/data bit 14 or enhanced pwm 1 output p1b. re7/ad15/ eccp2 (3) /p2a (3) bit 7 st/ttl (1) input/output port pin, address/data bit 15, enhanced capture 2 input/ compare 2 output/pwm 2 output or enhanced pwm 2 output p2a. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o or ccp/eccp modes and ttl buffers when in system bus or psp control modes. 2: valid for all PIC18F6525/6621 devices and pic18f8525/8621 devices when eccpmx is set. alternate assignments for p1b/p1c/p3b/p3c are rh7, rh6, rh5 and rh4, respectively. 3: valid for all PIC18F6525/6621 devices and pic18f8525/8621 devices in microcontroller mode when ccp2mx is not set. rc1 is the default assignment for eccp2/p2a for all devices in microcontroller mode when ccp2mx is set; rb3 is the alternate assignment for pic18f8525/8621 devices in operating modes except microcontroller mode when ccp2mx is not set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trise porte data direction control register 1111 1111 1111 1111 porte read porte pin/write porte data latch xxxx xxxx uuuu uuuu late read porte data latch/write porte data latch xxxx xxxx uuuu uuuu memcon (1) ebdis ? wait1 wait0 ? ? wm1 wm0 0-00 --00 0000 --00 pspcon (2) ibf obf ibov pspmode ? ? ? ? 0000 ---- 0000 ---- legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by porte. note 1: this register is unused on PIC18F6525/6621 devices and reads as ? 0 ?. 2: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 117 PIC18F6525/6621/8525/8621 10.6 portf, latf and trisf registers portf is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisf. setting a trisf bit (= 1 ) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisf bit (= 0 ) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latf register, read and write the latched output value for portf. portf is multiplexed with several analog peripheral functions, including the a/d converter inputs and comparator inputs, outputs and voltage reference. example 10-6: initializing portf figure 10-13: portf rf1/an6/c2out, rf2/an 7/c1out pins block diagram note 1: on a power-on reset, the rf6:rf0 pins are configured as inputs and read as ? 0 ?. 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 0x07 ; movwf cmcon ; turn off comparators movlw 0x0f ; movwf adcon1 ; set portf as digital i/o movlw 0xcf ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf0 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs port/comparator select data bus wr latf wr trisf data latch tris latch rd trisf q d q ck qd en comparator data out 0 1 q d q ck p n v dd v ss rd portf i/o pin or wr portf rd latf schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . analog input mode to a/d converter
PIC18F6525/6621/8525/8621 ds39612b-page 118 ? 2005 microchip technology inc. figure 10-14: rf6:rf3 and rf0 pins block diagram figure 10-15: rf7 pin block diagram data bus q d q ck q d q ck qd en p n wr latf wr trisf data latch tris latch rd trisf rd portf v ss v dd i/o pin analog input mode st input buffer to a/d converter or comparator input rd latf or wr portf note 1: i/o pins have diode protection to v dd and v ss . data bus wr latf wr trisf rd portf data latch tris latch rd trisf schmitt trigger input buffer i/o pin q d ck q d ck en qd en rd latf or wr portf note: i/o pins have diode protection to v dd and v ss . ttl input buffer ss input
? 2005 microchip technology inc. ds39612b-page 119 PIC18F6525/6621/8525/8621 table 10-11: portf functions table 10-12: summary of registers associated with portf name bit# buffer type function rf0/an5 bit 0 st input/output port pin or analog input. rf1/an6/c2out bit 1 st input/output port pin, analog input or comparator 2 output. rf2/an7/c1out bit 2 st input/output port pin, analog input or comparator 1 output. rf3/an8 bit 3 st input/output port pin or analog input/comparator input. rf4/an9 bit 4 st input/output port pin or analog input/comparator input. rf5/an10/cv ref bit 5 st input/output port pin, analog input/comparator input or comparator reference output. rf6/an11 bit 6 st input/output port pin or analog input/comparator input. rf7/ss bit 7 st/ttl input/output port pin or slave select pin for synchronous serial port. legend: st = schmitt trigger input, ttl = ttl input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisf portf data direction control register 1111 1111 1111 1111 portf read portf pin/write portf data latch x000 0000 u000 0000 latf read portf data latch/write portf data latch xxxx xxxx uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by portf.
PIC18F6525/6621/8525/8621 ds39612b-page 120 ? 2005 microchip technology inc. 10.7 portg, trisg and latg registers portg is a 6-bit wide port with 5 bidirectional pins (rg0:rg4) and one optional input only pin (rg5). the corresponding data direction register is trisg. setting a trisg bit (= 1 ) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisg bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latg) is also memory mapped. read-modify-write operations on the latg register, read and write the latched output value for portg. portg is multiplexed with both ccp/eccp and eusart functions (table 10-13). portg pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris reg- ister. this allows read-modify-write operations of the tris register without concern due to peripheral overrides. the sixth pin of portg (mclr /v pp /rg5) is a digital input pin. its operation is controlled by the mclre configuration bit in configuration register 3h (config3h<7>). in its default configuration (mclre = 1 ), the pin functions as the device master clear input. when selected as a port pin (mclre = 0 ), it functions as an input only pin; as such, it does not have trisg or latg bits associated with it. in either configuration, rg5 also functions as the programming voltage input during device programming. example 10-7: initializing portg figure 10-16: portg block diagram (peripheral output override) note: on a power-on reset, these pins are configured as digital inputs. note 1: on a power-on reset, rg5 is enabled as a digital input only if master clear functionality is disabled (mclre = 0 ). 2: if the device master clear is disabled, verify that either of the following is done to ensure proper entry into icsp mode: a.) disable low-voltage programming (config4l<2> = 0 ); or b.) make certain that rb5/kbi1/pgm is held low during entry into icsp. clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 0x04 ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as inputs portg/peripheral out select data bus wr latg wr trisg data latch tris latch rd trisg q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd portg peripheral data in i/o pin (1) or wr portg rd latg schmitt trigger tris override peripheral output logic tris override pin override peripheral rg0 yes eccp3 i/o rg1 yes usart1 async xmit, sync clock rg2 yes usart1 async rcv, sync data out rg3 yes ccp4 i/o rg4 yes ccp5 i/o enable (2) note 1: i/o pins have diode protection to v dd and v ss . 2: peripheral output enable is only active if peripheral select is active.
? 2005 microchip technology inc. ds39612b-page 121 PIC18F6525/6621/8525/8621 figure 10-17: mclr /v pp /rg5 pin block diagram table 10-13: portg functions table 10-14: summary of registers associated with portg mclr /v pp /rg5 data bus rd porta rd lata schmitt trigger mclre rd trisa qd en latch filter low-level mclr detect high-voltage detect internal mclr hv name bit# buffer type function rg0/eccp3/p3a bit 0 st input/output port pin, enhanced capture 3 input/compare 3 output/ pwm 3 output or enhanced pwm 3 output p3a. rg1/tx2/ck2 bit 1 st input/output port pin, addressable usart2 asynchronous transmit or addressable usart2 synchronous clock. rg2/rx2/dt2 bit 2 st input/output port pin, addressable usart2 asynchronous receive or addressable usart2 synchronous data. rg3/ccp4/p3d bit 3 st input/output port pin, capture 4 input/compare 4 output/pwm 4 output or enhanced pwm 3 output p3d. rg4/ccp5/p1d bit 4 st input/output port pin, capture 5 input/compare 5 output/pwm 5 output or enhanced pwm 1 output p1d. mclr /v pp /rg5 bit 5 st master clear input or programming voltage input (if mclr is enabled). input only port pin or programming voltage input (if mclr is disabled). legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portg ? ?rg5 (1) read portg pins/write portg data latch --xx xxxx --uu uuuu latg ? ? ? latg data output register ---x xxxx ---u uuuu trisg ? ? ? data direction control register for portg ---1 1111 ---1 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ? note 1: rg5 is available as an input only when mclr is disabled.
PIC18F6525/6621/8525/8621 ds39612b-page 122 ? 2005 microchip technology inc. 10.8 porth, lath and trish registers porth is an 8-bit wide, bidirectional i/o port. the cor- responding data direction register is trish. setting a trish bit (= 1 ) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trish bit (= 0 ) will make the corresponding porth pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the lath register, read and write the latched output value for porth. pins rh7:rh4 are multiplexed with analog inputs an15:an12. pins rh3:rh0 are multiplexed with the system bus as the external memory interface; they are the high-order address bits a19:a16. by default, pins rh7:rh4 are enabled as a/d inputs and pins rh3:rh0 are enabled as the system address bus. register adcon1 configures rh7:rh4 as i/o or a/d inputs. register memcon configures rh3:rh0 as i/o or system bus pins. example 10-8: initializing porth figure 10-18: rh3:rh0 pins block diagram in i/o mode figure 10-19: rh7:rh4 pins block diagram in i/o mode note: porth is available only on pic18f8525/ 8621 devices. note 1: on power-on reset, porth pins rh7:rh4 default to a/d inputs and read as ? 0 ?. 2: on power-on reset, porth pins rh3:rh0 default to system bus signals. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0fh ; movwf adcon1 ; movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs data bus wr lath wr trish rd porth data latch tris latch rd trish schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd lath or porth note 1: i/o pins have diode protection to v dd and v ss . data bus wr lath wr trish rd porth data latch tris latch rd trish schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd lath or porth to a/d converter note 1: i/o pins have diode protection to v dd and v ss .
? 2005 microchip technology inc. ds39612b-page 123 PIC18F6525/6621/8525/8621 figure 10-20: rh3:rh0 pins bloc k diagram in system bus mode to instruction register external enable address out drive system system bus control data bus wr lath wr trish rd porth data latch tris latch rd trish ttl input buffer i/o pin (1) q d ck q d ck en qd en rd lath or porth 0 1 port data instruction read note 1: i/o pins have diode protection to v dd and v ss .
PIC18F6525/6621/8525/8621 ds39612b-page 124 ? 2005 microchip technology inc. table 10-15: porth functions table 10-16: summary of registers associated with porth name bit# buffer type function rh0/a16 bit 0 st/ttl (1) input/output port pin or address bit 16 for external memory interface. rh1/a17 bit 1 st/ttl (1) input/output port pin or address bit 17 for external memory interface. rh2/a18 bit 2 st/ttl (1) input/output port pin or address bit 18 for external memory interface. rh3/a19 bit 3 st/ttl (1) input/output port pin or address bit 19 for external memory interface. rh4/an12/p3c (2) bit 4 st input/output port pin, analog input channel 12 or enhanced pwm output p3c. rh5/an13/p3b (2) bit 5 st input/output port pin, analog input channel 13 or enhanced pwm output p3b. rh6/an14/p1c (2) bit 6 st input/output port pin, analog input channel 14 or enhanced pwm output p1c. rh7/an15/p1b (2) bit 7 st input/output port pin, analog input channel 15 or enhanced pwm3 output p1b. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in system bus or parallel slave port mode. 2: valid only for pic18f8525/8621 devices when eccpmx is not set. the alternate assignments for p1b/p1c/p3b/p3c in all PIC18F6525/6621 devices and in pic18f8525/8621 devices when eccpmx is set are re6, re5, re4 and re3, respectively. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trish porth data direction control register 1111 1111 1111 1111 porth read porth pin/write porth data latch 0000 xxxx 0000 uuuu lath read porth data latch/write porth data latch xxxx xxxx uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 memcon (1) ebdis ? wait1 wait0 ? ? wm1 wm0 0-00 --00 0-00 --00 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by porth. note 1: this register is unused on PIC18F6525/6621 devices and reads as ? 0 ?.
? 2005 microchip technology inc. ds39612b-page 125 PIC18F6525/6621/8525/8621 10.9 portj, trisj and latj registers portj is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisj. setting a trisj bit (= 1 ) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisj bit (= 0 ) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latj) is also memory mapped. read-modify-write operations on the latj register, read and write the latched output value for portj. portj is multiplexed with the system bus as the external memory interface; i/o port functions are only available when the system bus is disabled. when operating as the external memory interface, portj provides the control signal to external memory devices. the rj5 pin is not multiplexed with any system bus functions. when enabling peripheral functions, care should be taken in defining tris bits for each portj pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corre- sponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris reg- ister. this allows read-modify-write of the tris register without concern due to peripheral overrides. example 10-9: initializing portj figure 10-21: portj block diagram in i/o mode note: portj is available only on pic18f8525/ 8621 devices. note: on a power-on reset, these pins are configured as digital inputs. clrf portj ; initialize portg by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as output ; rj7:rj6 as inputs data bus wr latj wr trisj rd portj data latch tris latch rd trisj schmitt trigger input buffer i/o pin (1) q d ck q d ck en qd en rd latj or portj note 1: i/o pins have diode protection to v dd and v ss .
PIC18F6525/6621/8525/8621 ds39612b-page 126 ? 2005 microchip technology inc. figure 10-22: rj4:rj0 pins bl ock diagram in system bus mode figure 10-23: rj7:rj6 pins blo ck diagram in system bus mode external enable control out drive system system bus control data bus wr latj wr trisj rd portj data latch tris latch rd trisj i/o pin (1) q d ck q d ck en qd en rd latj or portj 0 1 port data note 1: i/o pins have diode protection to v dd and v ss . wm = 01 ub /lb out drive system system bus control data bus wr latj wr trisj rd portj data latch tris latch rd trisj i/o pin (1) q d ck q d ck en qd en rd latj or portj 0 1 port data note 1: i/o pins have diode protection to v dd and v ss .
? 2005 microchip technology inc. ds39612b-page 127 PIC18F6525/6621/8525/8621 table 10-17: portj functions table 10-18: summary of registers associated with portj name bit# buffer type function rj0/ale bit 0 st input/output port pin or address latch enable control for external memory interface. rj1/oe bit 1 st input/output port pin or output enable control for external memory interface. rj2/wrl bit 2 st input/output port pin or write low byte control for external memory interface. rj3/wrh bit 3 st input/output port pin or write high byte control for external memory interface. rj4/ba0 bit 4 st input/output port pin or byte address 0 control for external memory interface. rj5/ce bit 5 st input/output port pin or chip enable control for external memory interface. rj6/lb bit 6 st input/output port pin or lower byte select control for external memory interface. rj7/ub bit 7 st input/output port pin or upper byte select control for external memory interface. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portj read portj pin/write portj data latch xxxx xxxx uuuu uuuu latj latj data output register xxxx xxxx uuuu uuuu trisj data direction control register for portj 1111 1111 1111 1111 legend: x = unknown, u = unchanged
PIC18F6525/6621/8525/8621 ds39612b-page 128 ? 2005 microchip technology inc. 10.10 parallel slave port portd also operates as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (pspcon<4>) is set. it is asynchronously readable and writable by the external world through rd control input pin, re0/rd and wr control input pin, re1/wr . the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). the a/d port configuration bits, pcfg2:pcfg0 (adcon1<2:0>), must be set, which will configure pins re2:re0 as digital i/o. a write to the psp occurs when both the cs and wr lines are first detected low. a read from the psp occurs when both the cs and rd lines are first detected low. the porte i/o pins become control inputs for the micro- processor port when bit pspmode (pspcon<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs) and the adcon1 is configured for digital i/o. in this mode, the input buffers are ttl. figure 10-24: portd and porte block diagram (parallel slave port) note: for pic18f8525/8621 devices, the parallel slave port is available only in microcontroller mode. data bus wr latd rdx q d ck en qd en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch tris latch
? 2005 microchip technology inc. ds39612b-page 129 PIC18F6525/6621/8525/8621 register 10-1: pspcon: parallel slave port control register (1) figure 10-25: parallel slave port write waveforms r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented: read as ? 0 ? note 1: enabled only in microcontroller mode for pic18f8525/8621 devices. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0>
PIC18F6525/6621/8525/8621 ds39612b-page 130 ? 2005 microchip technology inc. figure 10-26: parallel slave port read waveforms table 10-19: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu latd latd data output bits xxxx xxxx uuuu uuuu trisd portd data direction bits 1111 1111 1111 1111 porte read porte pin/write porte data latch xxxx xxxx uuuu uuuu late late data output bits xxxx xxxx uuuu uuuu trise porte data direction bits 1111 1111 1111 1111 pspcon (1) ibf obf ibov pspmode ? ? ? ? 0000 ---- 0000 ---- intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 131 PIC18F6525/6621/8525/8621 11.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt-on-overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock figure 11-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register (register 11-1) is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 132 ? 2005 microchip technology inc. figure 11-1: timer0 block diagram in 8-bit mode figure 11-2: timer0 block diagram in 16-bit mode note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l
? 2005 microchip technology inc. ds39612b-page 133 PIC18F6525/6621/8525/8621 11.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 11.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , x and so on) will clear the prescaler count. 11.2.1 switching prescaler assignment the prescaler assignment is fully under software control, (i.e., it can be changed ?on-the-fly? during program execution). 11.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0ie bit must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. 11.4 16-bit mode timer reads and writes tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 11-2). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 low byte register xxxx xxxx uuuu uuuu tmr0h timer0 high byte register 0000 0000 uuuu uuuu intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ? trisa6 (1) porta data direction register -111 1111 -111 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by timer0. note 1: ra6 and associated bits are configured as port pins in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes.
PIC18F6525/6621/8525/8621 ds39612b-page 134 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 135 PIC18F6525/6621/8525/8621 12.0 timer1 module the timer1 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from eccp module special event trigger figure 12-1 is a simplified block diagram of the timer1 module. register 12-1 details the timer1 control register. this register controls the operating mode of the timer1 module and contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. register 12-1: t1con: timer1 control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 unimplemented: read as ? 0 ? bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 136 ? 2005 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs = 0 , timer1 increments every instruc- tion cycle. when tmr1cs = 1 , timer1 increments on every rising edge of the external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t13cki pins become inputs. that is, the trisc<1:0> value is ignored and the pins are read as ? 0 ?. timer1 also has an internal ?reset input?. this reset can be generated by the eccp1 or eccp2 special event trigger. this is discussed in detail in section 12.4 ?resetting timer1 using an eccp special trigger output? . figure 12-1: timer1 block diagram figure 12-2: timer1 block diag ram: 16-bit read/write mode tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 sleep input f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr eccp special event trigger t1oscen enable oscillator (1) t1osc interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. t1osi t1oso/t13cki timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/t13cki t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l clr eccp special event trigger
? 2005 microchip technology inc. ds39612b-page 137 PIC18F6525/6621/8525/8621 12.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low-power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator 12.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing the tmr1 interrupt enable bit, tmr1ie (pie1<0>). 12.4 resetting timer1 using an eccp special trigger output if either the eccp1 or eccp2 module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1. the trigger for eccp2 will also start an a/d conversion if the a/d module is enabled. timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from eccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. 12.5 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. table 12-1: capacitor selection for the alternate oscillator (2-4) osc type freq c1 c2 lp 32 khz 15-22 pf (1) 15-22 pf (1) crystal tested 32.768 khz note 1: microchip suggests 33 pf as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal pic18f6x2x/8x2x t1osi t1oso 32.768 khz 33 pf 33 pf note: the special event triggers from the eccp1 module will not set interrupt flag bit tmr1if (pir1<0>).
PIC18F6525/6621/8525/8621 ds39612b-page 138 ? 2005 microchip technology inc. 12.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.2 ?timer1 oscillator? ) gives users the option to include rtc functionality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 register pair to overflow, triggers the interrupt and calls the routine which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it. the simplest method is to set the most signifi- cant bit of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. example 12-1: implementing a real-time clock using a timer1 interrupt service rtcinit movlw 0x80 ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done movlw .01 ; reset hours to 1 movwf hours return ; done
? 2005 microchip technology inc. ds39612b-page 139 PIC18F6525/6621/8525/8621 table 12-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr1l timer1 register low byte xxxx xxxx uuuu uuuu tmr1h timer1 register high byte xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 140 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 141 PIC18F6525/6621/8525/8621 13.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match of pr2 mssp module optional use of tmr2 output to generate clock shift timer2 has a control register shown in register 13-1. timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 13-1 is a simplified block diagram of the timer2 module. register 13-1 shows the timer2 control register. the prescaler and postscaler selection of timer2 are controlled by this register. 13.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the eccp module. the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt, latched in flag bit tmr2if (pir1<1>). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: time r2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps3:t2outps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 142 ? 2005 microchip technology inc. 13.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 13.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock. figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the mssp module as a baud clock. t2outps3:t2outps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 143 PIC18F6525/6621/8525/8621 14.0 timer3 module the timer3 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from eccp module trigger figure 14-1 is a simplified block diagram of the timer3 module. register 14-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp/eccp clock source. register 12-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen) which can be a clock source for timer3. register 14-1: t3con: time r3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 11 = timer3 and timer4 are the clock sources for eccp1 through ccp5 10 = timer3 and timer4 are the clock sources for eccp3 through ccp5; timer1 and timer2 are the clock sources for eccp1 and eccp2 01 = timer3 and timer4 are the clock sources for eccp2 through ccp5; timer1 and timer2 are the clock sources for eccp1 00 = timer1 and timer2 are the clock sources for eccp1 through ccp5 bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 144 ? 2005 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs = 0 , timer3 increments every instruc- tion cycle. when tmr3cs = 1 , timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t13cki pins become inputs. that is, the trisc<1:0> value is ignored and the pins are read as ? 0 ?. timer3 also has an internal ?reset input?. this reset can be generated by the eccp module ( section 14.0 ?timer3 module? ). figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram co nfigured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. t13cki clr eccp special event trigger t3ccpx timer3 tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t13cki clr eccp special event trigger t3ccpx to timer1 clock input note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l set tmr3if flag bit on overflow
? 2005 microchip technology inc. ds39612b-page 145 PIC18F6525/6621/8525/8621 14.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. the oscillator is a low- power oscillator rated up to 200 khz. see section 12.0 ?timer1 module? for further details. 14.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled/disabled by setting/clearing tmr3 interrupt enable bit, tmr3ie (pie2<1>). 14.4 resetting timer3 using an eccp special trigger output if either the eccp1 or eccp2 module is configured in compare mode to generate a special event trigger (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from eccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer3. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the eccp module will not set interrupt flag bit, tmr3if (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 -0-0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 -1-1 1111 tmr3l timer3 register low byte xxxx xxxx uuuu uuuu tmr3h timer3 register high byte xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer3 module.
PIC18F6525/6621/8525/8621 ds39612b-page 146 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 147 PIC18F6525/6621/8525/8621 15.0 timer4 module the timer4 module timer has the following features: 8-bit timer (tmr4 register) 8-bit period register (pr4) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr4 match of pr4 timer4 has a control register shown in register 15-1. timer4 can be shut off by clearing control bit, tmr4on (t4con<2>), to minimize power consumption. the prescaler and postscaler selection of timer4 are also controlled by this register. figure 15-1 is a simplified block diagram of the timer4 module. 15.1 timer4 operation timer4 can be used as the pwm time base for the pwm mode of the ccp module. the tmr4 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t4ckps1:t4ckps0 (t4con<1:0>). the match output of tmr4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr4 interrupt, latched in flag bit tmr4if (pir3<3>). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr4 register a write to the t4con register any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr4 is not cleared when t4con is written. register 15-1: t4con: time r4 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 t4outps3:t4outps0 : timer4 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr4on : timer4 on bit 1 = timer4 is on 0 = timer4 is off bit 1-0 t4ckps1:t4ckps0 : timer4 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 148 ? 2005 microchip technology inc. 15.2 timer4 interrupt the timer4 module has an 8-bit period register, pr4, which is both readable and writable. timer4 increments from 00h until it matches pr4 and then resets to 00h on the next increment cycle. the pr4 register is initialized to ffh upon reset. 15.3 output of tmr4 the output of tmr4 (before the postscaler) is used only as a pwm time base for the ccp modules. it is not used as a baud rate clock for the mssp, as is the timer2 output. figure 15-1: timer4 block diagram table 15-1: registers associated with timer4 as a timer/counter comparator tmr4 sets flag tmr4 output reset postscaler prescaler pr4 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr4if t4outps3:t4outps0 t4ckps1:t4ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --00 0000 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 tmr4 timer4 register 0000 0000 0000 0000 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 -000 0000 pr4 timer4 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer4 module.
? 2005 microchip technology inc. ds39612b-page 149 PIC18F6525/6621/8525/8621 16.0 capture/compare/pwm (ccp) modules PIC18F6525/6621/8525/8621 devices all have a total of five ccp (capture/compare/pwm) modules. two of these (ccp4 and ccp5) implement standard capture, compare and pulse-width modulation (pwm) modes and are discussed in this section. the other three modules (eccp1, eccp2, eccp3) implement standard capture and compare modes, as well as enhanced pwm modes. these are discussed in section 17.0 ?enhanced capture/compare/pwm (eccp) module? . each ccp/eccp module contains a 16-bit register which can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. for the sake of clarity, all ccp module opera- tion in the following sections is described with respect to ccp4, but is equally applicable to ccp5. capture and compare operations described in this chapter apply to all standard and enhanced ccp modules. the operations of pwm mode described in section 16.4 ?pwm mode? apply to ccp4 and ccp5 only. register 16-1: ccpxcon register (ccp4 and ccp5 modules) note: throughout this section and section 17.0 ?enhanced capture/compare/pwm (eccp) module? , references to register and bit names that may be associated with a specific ccp module are referred to generically by the use of ?x? or ?y? in place of the specific module number. thus, ?ccpxcon? might refer to the control register for ccp4 or ccp5, or eccp1, eccp2 or eccp3. ?ccpxcon? is used throughout these sections to refer to the module control register, regardless of whether the ccp module is a standard or enhanced implementation. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 for ccp module x capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle. the eight most significant bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccp module x mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode; initialize ccp pin low; on compare match, force ccp pin high (ccpif bit is set) 1001 = compare mode; initialize ccp pin high; on compare match, force ccp pin low (ccpif bit is set) 1010 = compare mode; generate software interrupt on compare match (ccpif bit is set, ccp pin reflects i/o state) 1011 = reserved 11xx = pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 150 ? 2005 microchip technology inc. 16.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register in turn is com- prised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 16.1.1 ccp modules and timer resources the ccp/eccp modules utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. table 16-1: ccp mode ? timer resource the assignment of a particular timer to a module is determined by the timer-to-ccp enable bits in the t3con register (register 14-1, page 143). depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 16-1. figure 16-1: ccp and timer interconnect configurations ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 or timer4 tmr1 ccp5 tmr2 tmr3 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 t3ccp<2:1> = 00 t3ccp<2:1> = 01 t3ccp<2:1> = 10 t3ccp<2:1> = 11 timer1 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer3 and timer4 are not available. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 only (depending on selected mode). all other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/ compare or pwm modes. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 and eccp2 only (depending on the mode selected for each module). both modules may use a timer as a common time base if they are both in capture/compare or pwm modes. the other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/ compare or pwm modes. timer3 is used for all capture and compare operations for all ccp modules. timer4 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer1 and timer2 are no t available.
? 2005 microchip technology inc. ds39612b-page 151 PIC18F6525/6621/8525/8621 16.2 capture mode in capture mode, the ccpr4h:ccpr4l register pair captures the 16-bit value of the tmr1 or tmr3 regis- ters when an event occurs on pin rg3/ccp4/p1d. an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by the mode select bits, ccp4m3:ccp4m0 (ccp4con<3:0>). when a capture is made, the interrupt request flag bit ccp4if (pir3<1>) is set; it must be cleared in software. if another capture occurs before the value in register ccpr4 is read, the old captured value is overwritten by the new captured value. 16.2.1 ccp pin configuration in capture mode, the rg3/ccp4/p1d pin should be configured as an input by setting the trisg<3> bit. 16.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register (see section 16.1.1 ?ccp modules and timer resources? ). 16.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp4ie (pie3<1>) clear to avoid false interrupts and should clear the flag bit, ccp4if, following any such change in operating mode. 16.2.4 ccp prescaler there are four prescaler settings in capture mode; they are specified as part of the operating mode selected by the mode select bits (ccp4m3:ccp4m0). whenever the ccp module is turned off or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 16-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 16-1: changing between capture prescalers figure 16-2: capture mode operat ion block diagram note: if the rg3/ccp4/p1d is configured as an output, a write to the port can cause a capture condition. clrf ccp4con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp4con ; load ccp1con with ; this value ccpr4h ccpr4l tmr1h tmr1l set flag bit ccp4if tmr3 enable q?s ccp1con<3:0> rg3/ccp4/p1d pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2
PIC18F6525/6621/8525/8621 ds39612b-page 152 ? 2005 microchip technology inc. 16.3 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccp4 pin can be: driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccp4m3:ccp4m0). at the same time, the interrupt flag bit ccp4if is set. 16.3.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 16.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 16.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccp4m3:ccp4m0 = 1010 ), the ccp4 pin is not affected. only a ccp interrupt is generated if enabled and the ccp4ie bit is set. 16.3.4 special event trigger although shown in figure 16-3, the compare on match special event triggers are not implemented on ccp4 or ccp5; they are only available on eccp1 and eccp2. their operation is discussed in detail in section 17.2.1 ?special event trigger? . figure 16-3: compare mode operation block diagram note: clearing the ccp4con register will force the rg3/ccp4/p1d compare output latch to the default low level. this is not the portg i/o data latch. ccpr4h ccpr4l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp4if match rg3/ccp4/p1d trisg<3> ccp4con<3:0> mode select output enable tmr3h tmr3l t3ccp2 1 0 (eccp1 and eccp2 only) pin
? 2005 microchip technology inc. ds39612b-page 153 PIC18F6525/6621/8525/8621 table 16-2: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ? ? ri to pd por bor 0--1 11qq 0--q qquu pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir2 ? cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 ---0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 ---0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 ---1 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 trisb portb data direction register 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 trise porte data direction register 1111 1111 1111 1111 trisg ? ? ? portg data direction register ---1 1111 ---1 1111 tmr1l timer1 register low byte xxxx xxxx uuuu uuuu tmr1h timer1 register high byte xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu tmr3h timer3 register high byte xxxx xxxx uuuu uuuu tmr3l timer3 register low byte xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu ccpr1l enhanced capture/compar e/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr2l enhanced capture/compar e/pwm register 2 low byte xxxx xxxx uuuu uuuu ccpr2h enhanced capture/compare/pwm register 2 high byte xxxx xxxx uuuu uuuu ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 0000 0000 ccpr3l enhanced capture/compar e/pwm register 3 low byte xxxx xxxx uuuu uuuu ccpr3h enhanced capture/compare/pwm register 3 high byte xxxx xxxx uuuu uuuu ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 0000 0000 ccpr4l capture/compare/pwm register 4 low byte xxxx xxxx uuuu uuuu ccpr4h capture/compare/pwm register 4 high byte xxxx xxxx uuuu uuuu ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 --00 0000 --00 0000 ccpr5l capture/compare/pwm register 5 low byte xxxx xxxx uuuu uuuu ccpr5h capture/compare/pwm register 5 high byte xxxx xxxx uuuu uuuu ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by capture and compare, timer1 or timer3. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 154 ? 2005 microchip technology inc. 16.4 pwm mode in pulse-width modulation (pwm) mode, the ccp4 pin produces up to a 10-bit resolution pwm output. since the ccp4 pin is multiplexed with the portg data latch, the trisg<3> bit must be cleared to make the ccp4 pin an output. figure 16-4 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 16.4.3 ?setup for pwm operation? . figure 16-4: simplified pwm block diagram a pwm output (figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 16-5: pwm output 16.4.1 pwm period the pwm period is specified by writing to the pr2 (pr4) register. the pwm period can be calculated using the following formula: equation 16-1: pwm frequency is defined as 1/[pwm period]. when tmr2 (tmr4) is equal to pr2 (pr2), the following three events occur on the next increment cycle: tmr2 (tmr4) is cleared the ccp4 pin is set (exception: if pwm duty cycle = 0%, the ccp4 pin will not be set) the pwm duty cycle is latched from ccpr4l into ccpr4h 16.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr4l register and to the ccp4con<5:4> bits. up to 10-bit resolution is available. the ccpr4l contains the eight msbs and the ccp4con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr4l:ccp4con<5:4>. the following equation is used to calculate the pwm duty cycle in time: equation 16-2: ccpr4l and ccp4con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr4h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr4h is a read-only register. the ccpr4h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr4h and 2-bit latch match tmr2, con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp4 pin is cleared. note: clearing the ccp4con register will force the ccp4 pwm output latch to the default low level. this is not the portg i/o data latch. ccpr4l ccpr4h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisg<3> rg3/ccp4 note 1: 8-bit tmr2 or tmr4 is concatenated with 2-bit internal q clock, or 2 bits of the prescaler, to create 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 and timer4 postscalers (see section 13.0 ?timer2 module? ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm duty cycle = (ccpr4l:ccp4con<5:4>) t osc (tmr2 prescale value)
? 2005 microchip technology inc. ds39612b-page 155 PIC18F6525/6621/8525/8621 the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 16-3: 16.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. select tmr2 or tmr4 by setting or clearing the t3ccp2:t3ccp1 bits in the t3con register. 2. set the pwm period by writing to the pr2 or pr4 register 3. set the pwm duty cycle by writing to the ccpr4l register and ccp4con<5:4> bits. 4. make the ccp4 pin an output by clearing the trisg<3> bit. 5. set tmr2 or tmr4 prescale value, enable timer2 or timer4 by writing to t2con or t4con. 6. configure the ccp4 module for pwm operation. table 16-3: example pwm frequencies and resolutions at 40 mhz note: if the pwm duty cycle value is longer than the pwm period, the ccp4 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 14 12 10 8 7 6.58
PIC18F6525/6621/8525/8621 ds39612b-page 156 ? 2005 microchip technology inc. table 16-4: registers associated with pwm, timer2 and timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ? ? ri to pd por bor 0--1 11qq 0--q qquu pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir2 ? cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 ---0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 ---0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 ---1 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 tmr2 timer2 register 0000 0000 0000 0000 pr2 timer2 period register 1111 1111 1111 1111 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu tmr4 timer4 register 0000 0000 uuuu uuuu pr4 timer4 period register 1111 1111 uuuu uuuu t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 uuuu uuuu ccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr2l enhanced capture/compare/pwm register 2 low byte xxxx xxxx uuuu uuuu ccpr2h enhanced capture/compare/pwm register 2 high byte xxxx xxxx uuuu uuuu ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 0000 0000 ccpr3l enhanced capture/compare/pwm register 3 low byte xxxx xxxx uuuu uuuu ccpr3h enhanced capture/compare/pwm register 3 high byte xxxx xxxx uuuu uuuu ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 0000 0000 ccpr4l capture/compare/pwm register 4 low byte xxxx xxxx uuuu uuuu ccpr4h capture/compare/pwm register 4 high byte xxxx xxxx uuuu uuuu ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 --00 0000 --00 0000 ccpr5l capture/compare/pwm register 5 low byte xxxx xxxx uuuu uuuu ccpr5h capture/compare/pwm register 5 high byte xxxx xxxx uuuu uuuu ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm, timer2 or timer4. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 157 PIC18F6525/6621/8525/8621 17.0 enhanced capture/ compare/pwm (eccp) module the enhanced ccp (eccp) modules differ from the standard ccp modules by the addition of enhanced pwm capabilities. these allow for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in section 17.4 ?enhanced pwm mode? . except for the addition of the special event trigger, capture and compare functions of the eccp module are the same as the standard ccp module. the prototype control register for the enhanced ccp module is shown in register 17-1. in addition to the expanded range of modes available through the ccpxcon register, the eccp modules each have two additional registers associated with enhanced pwm operation and auto-shutdown features. they are: eccpxdel (dead-band delay) eccpxas (auto-shutdown configuration) register 17-1: ccpxcon register (eccp1, eccp2 and eccp3 modules) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxm1 pxm0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 pxm1:pxm0: enhanced pwm output configuration bits if ccpxm3:ccpxm2 = 00 , 01 , 10 : xx = pxa assigned as capture/compare input/output; pxb, pxc, pxd assigned as port pins if ccpxm3:ccpxm2 = 11 : 00 = single output: pxa modulated; pxb, pxc, pxd assigned as port pins 01 = full-bridge output forward: p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output: p1a, p1b modulated with dead-band control; p1c, p1d assigned as port pins 11 = full-bridge output reverse: p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the 10-bit pwm duty cycle. the eight msbs of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : enhanced ccp mode select bits 0000 = capture/compare/pwm off (resets eccpx module) 0001 = reserved 0010 = compare mode, toggle output on match 0011 = capture mode 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize eccp pin low, set output on compare match (set ccpxif) 1001 = compare mode, initialize eccp pin high, clear output on compare match (set ccpxif) 1010 = compare mode, generate software interrupt only, eccp pin reverts to i/o state 1011 = compare mode, trigger special event (eccp resets tmr1 or tmr3, sets ccxif bit, eccp2 trigger starts a/d conversion if a/d module is enabled) (1) 1100 = pwm mode; pxa, pxc active-high; pxb, pxd active-high 1101 = pwm mode; pxa, pxc active-high; pxb, pxd active-low 1110 = pwm mode; pxa, pxc active-low; pxb, pxd active-high 1111 = pwm mode; pxa, pxc active-low; pxb, pxd active-low note 1: implemented only for eccp1 and eccp2; same as ? 1010 ? for eccp3. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 158 ? 2005 microchip technology inc. 17.1 eccp outputs and configuration each of the enhanced ccp modules may have up to four pwm outputs, depending on the selected operating mode. these outputs, designated pxa through pxd, are multiplexed with various i/o pins. some eccp pin assignments are constant, while others change based on device configuration. for those pins that do change, the controlling bits are: ccp2mx configuration bit (config3h<0>) eccpmx configuration bit (config3h<1>) program memory mode (set by configuration bits config3l<1:0>) the pin assignments for the enhanced ccp modules are summarized in table 17-1, table 17-2 and table 17-3. to configure the i/o pins as pwm outputs, the proper pwm mode must be selected by setting the pxmx and ccpxmx bits (ccpxcon<7:6> and <3:0>, respectively). the appropriate tris direction bits for the corresponding port pins must also be set as outputs. 17.1.1 use of ccp4 and ccp5 with eccp1 and eccp3 only the eccp2 module has four dedicated output pins available for use. assuming that the i/o ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other ccp module. eccp1 and eccp3, on the other hand, only have three dedicated output pins: eccpx/pxa, pxb and pxc. whenever these modules are configured for quad pwm mode, the pin normally used for ccp4 or ccp5 becomes the d output pins for eccp3 and eccp1, respectively. the ccp4 and ccp5 modules remain functional but their outputs are overridden. 17.1.2 eccp module outputs and program memory modes for pic18f8525/8621 devices, the program memory mode of the device ( section 4.1.1 ?PIC18F6525/6621/ 8525/8621 program memory modes? ) impacts both pin multiplexing and the operation of the module. the eccp2 input/output (eccp2/p2a) can be multi- plexed to one of three pins. by default, this is rc1 for all devices. in this case, the default occurs when ccp2mx is set and the device is operating in micro- controller mode. with pic18f8525/8621 devices, three other options exist. when ccp2mx is not set (= 0 ) and the device is in microcontroller mode, eccp2/p2a is multiplexed to re7; in all other program memory modes, it is multiplexed to rb3. the final option is for ccp2mx to be set while the device is operating in one of the three other program memory modes. in this case, eccp1 and eccp3 oper- ate as compatible (i.e., single output) ccp modules. the pins used by their other outputs (pxb through pxd) are available for other multiplexed functions. eccp2 continues to operate as an enhanced ccp module regardless of the program memory mode. table 17-1: pin config urations for eccp1 eccp mode ccp1con configuration rc2 re6 re5 rg4 rh7 rh6 all PIC18F6525/6621 devices: compatible ccp 00xx 11xx eccp1 re6 re5 rg4/ccp5 n/a n/a dual pwm 10xx 11xx p1a p1b re5 rg4/ccp5 n/a n/a quad pwm x1xx 11xx p1a p1b p1c p1d n/a n/a pic18f8525/8621 devices, eccpmx = 1 , microcontroller mode: compatible ccp 00xx 11xx eccp1 re6/ad14 re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a p1b re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 quad pwm x1xx 11xx p1a p1b p1c p1d rh7/an15 rh6/an14 pic18f8525/8621 devices, eccpmx = 0 , microcontroller mode: compatible ccp 00xx 11xx eccp1 re6/ad14 re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a re6/ad14 re5/ad13 rg4/ccp5 p1b rh6/an14 quad pwm x1xx 11xx p1a re6/ad14 re5/ad13 p1d p1b p1c pic18f8525/8621 devices, eccpmx = 1 , all other program memory modes: compatible ccp 00xx 11xx eccp1 re6/ad14 re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 legend: x = don?t care, n/a = not available. shaded cells indica te pin assignments not used by eccp1 in a given mode. note 1: with eccp1 in quad pwm mode, ccp5?s output is overridden by p1d; otherwise ccp5 is fully operational.
? 2005 microchip technology inc. ds39612b-page 159 PIC18F6525/6621/8525/8621 table 17-2: pin config urations for eccp2 table 17-3: pin config urations for eccp3 eccp mode ccp2con configuration rb3 rc1 re7 re2 re1 re0 all devices, ccp2mx = 1 , microcontroller mode: compatible ccp 00xx 11xx rb3/int3 eccp2 re7 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 p2a re7 p2b re1 re0 quad pwm x1xx 11xx rb3/int3 p2a re7 p2b p2c p2d all devices, ccp2mx = 0 , microcontroller mode: compatible ccp 00xx 11xx rb3/int3 rc1/t1os1 eccp2 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 rc1/t1os1 p2a p2b re1 re0 quad pwm x1xx 11xx rb3/int3 rc1/t1os1 p2a p2b p2c p2d pic18f8525/8621 devices, ccp2mx = 0 , all other program memory modes: compatible ccp 00xx 11xx eccp2 rc1/t1os1 re7/ad15 re2/cs re1/wr re0/rd dual pwm 10xx 11xx p2a rc1/t1os1 re7/ad15 p2b re1/wr re0/rd quad pwm x1xx 11xx p2a rc1/t1os1 re7/ad15 p2b p2c p2d legend: x = don?t care. shaded cells indicate pin assignments not used by eccp2 in a given mode. eccp mode ccp3con configuration rg0 re4 re3 rg3 rh5 rh4 all PIC18F6525/6621 devices: compatible ccp 00xx 11xx eccp3 re4 re3 rg3/ccp4 n/a n/a dual pwm 10xx 11xx p3a p3b re3 rg3/ccp4 n/a n/a quad pwm x1xx 11xx p3a p3b p3c p3d n/a n/a pic18f8525/8621 devices, eccpmx = 1 , microcontroller mode: compatible ccp 00xx 11xx eccp3 re4/ad12 re3/ad11 rg3/ccp4 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a p3b re3/ad11 rg3/ccp4 rh5/an13 rh4/an12 quad pwm x1xx 11xx p3a p3b p3c p3d rh5/an13 rh4/an12 pic18f8525/8621 devices, eccpmx = 0 , microcontroller mode: compatible ccp 00xx 11xx eccp3 re6/ad14 re5/ad13 rg3/ccp4 rh7/an15 rh6/an14 dual pwm 10xx 11xx p3a re6/ad14 re5/ad13 rg3/ccp4 p3b rh6/an14 quad pwm x1xx 11xx p3a re6/ad14 re5/ad13 p3d p3b p3c pic18f8525/8621 devices, eccpmx = 1 , all other program memory modes: compatible ccp 00xx 11xx eccp3 re6/ad14 re5/ad13 rg3/ccp4 rh7/an15 rh6/an14 legend: x = don?t care, n/a = not available. shaded cells indicate pin assignments not used by eccp3 in a given mode. note 1: with eccp3 in quad pwm mode, ccp4?s output is ov erridden by p1d; otherwise ccp4 is fully operational.
PIC18F6525/6621/8525/8621 ds39612b-page 160 ? 2005 microchip technology inc. 17.1.3 eccp modules and timer resources like the standard ccp modules, the eccp modules can utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available for modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. additional details on timer resources are provided in section 16.1.1 ?ccp modules and timer resources? . 17.2 capture and compare modes except for the operation of the special event trigger discussed below, the capture and compare modes of the eccp module are identical in operation to that of ccp4. these are discussed in detail in section 16.2 ?capture mode? and section 16.3 ?compare mode? . 17.2.1 special event trigger in this mode, an internal hardware trigger is generated in compare mode, on a match between the ccpr register pair and the selected timer. this can be used in turn to initiate an action. the special event trigger output of either eccp1 or eccp2 resets the tmr1 or tmr3 register pair, depending on which timer resource is currently selected. this allows the ccprx register to effectively be a 16-bit programmable period register for timer1 or timer3. in addition, the eccp2 special event trigger will also start an a/d conversion if the a/d module is enabled. the triggers are not implemented for eccp3, ccp4 or ccp5. selecting the special event mode (ccpxm3:ccpxm0 = 1011 ) for these modules has the same effect as selecting the compare with software interrupt mode (ccpxm3:ccpxm0 = 1010 ). 17.3 standard pwm mode when configured in single output mode, the eccp module functions identically to the standard ccp module in pwm mode as described in section 16.4 ?pwm mode? . this is also sometimes referred to as ?compatible ccp? mode as in tables 17-1 through 17-3. 17.4 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is a backward compatible version of the standard ccp module and offers up to four outputs, designated pxa through pxd. users are also able to select the polarity of the signal (either active-high or active-low). the module?s output mode and polarity are configured by setting the pxm1:pxm0 and ccpxm3ccpxm0 bits of the ccpxcon register (ccpxcon<7:6> and ccpxcon<3:0>, respectively). for the sake of clarity, enhanced pwm mode operation is described generically throughout this section with respect to eccp1 and tmr2 modules. control register names are presented in terms of eccp1. all three enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. tmr2 or tmr4 can be selected for pwm operation by selecting the proper bits in t3con. figure 17-1 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when timer2 resets) in order to prevent glitches on any of the outputs. the exception is the pwm delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffer- ing, the module waits until the assigned timer resets instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate tris bits for output. 17.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the equation: equation 17-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the eccp1 pin is set (if pwm duty cycle = 0%, the eccp1 pin will not be set) the pwm duty cycle is copied from ccpr1l into ccpr1h note: the special event trigger from eccp2 will not set the timer1 or timer3 interrupt flag bits. note: when setting up single output pwm opera- tions, users are free to use either of the processes described in section 16.4.3 ?setup for pwm operation? or section 17.4.9 ?setup for pwm opera- tion? . the latter is more generic but will work for either single or multi-output pwm. note: the timer2 postscaler (see section 13.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value)
? 2005 microchip technology inc. ds39612b-page 161 PIC18F6525/6621/8525/8621 figure 17-1: simplified block diagram of the enhanced pwm module 17.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccprxl:ccpxcon<5:4>. the pwm duty cycle is calculated by the equation: equation 17-2: ccpr1l and ccp1con<5:4> can be written to at any time but the duty cycle value is not copied into ccpr1h until a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccprxh register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm opera- tion. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or two bits of the tmr2 prescaler, the eccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 17-3: table 17-4: example pwm frequencies and resolutions at 40 mhz ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers ccp1con<5:4> clear timer, set eccp1 pin and latch d.c. note 1: the 8-bit tmr2 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisx eccp1/p1a trisx p1b trisx trisx p1d output controller p1m1<1:0> 2 ccp1m<3:0> 4 eccp1del eccp1/p1a p1b p1c p1d p1c pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the eccp1 pin will not be cleared. ( ) pwm resolution (max) = f osc f pwm log log(2) bits pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58
PIC18F6525/6621/8525/8621 ds39612b-page 162 ? 2005 microchip technology inc. 17.4.3 pwm output configurations the p1m1:p1m0 bits in the ccp1con register allow one of four configurations: single output half-bridge output full-bridge output, forward mode full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 17.4 ?enhanced pwm mode? . the half-bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 17-2. figure 17-2: pwm output relationships (active-high state) 0 period 00 10 01 11 signal pr2 + 1 ccp1con <7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay delay
? 2005 microchip technology inc. ds39612b-page 163 PIC18F6525/6621/8525/8621 figure 17-3: pwm output relationships (active-low state) 17.4.4 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the pwm output sig- nal is output on the p1a pin, while the complementary pwm output signal is output on the p1b pin (figure 17-4). this mode can be used for half-bridge applications, as shown in figure 17-5, or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. the value of bits pdc6:pdc0 sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 17.4.6 ?programmable dead-band delay? for more details on dead-band delay operations. since the p1a and p1b outputs are multiplexed with the portc<2> and porte<6> data latches, the trisc<2> and trise<6> bits must be cleared to configure p1a and p1b as outputs. figure 17-4: half-bridge pwm output 0 period 00 10 01 11 signal pr2 + 1 ccp1con <7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) delay = 4 * t osc * (eccp1del<6:0>) note 1: dead-band delay is programmed us ing the eccp1del register ( section 17.4.6 ?programmable dead-band delay? ). period duty cycle td td (1) p1a (2) p1b (2) td = dead band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high.
PIC18F6525/6621/8525/8621 ds39612b-page 164 ? 2005 microchip technology inc. figure 17-5: examples of half-bri dge output mode applications pic18f6x2x/8x2x p1a p1b fet driver fet driver v+ v- load + v - + v - fet driver fet driver v+ v- load fet driver fet driver pic18f6x2x/8x2x p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit
? 2005 microchip technology inc. ds39612b-page 165 PIC18F6525/6621/8525/8621 17.4.5 full-bridge mode in full-bridge output mode, four pins are used as outputs; however, only two outputs are active at a time. in the forward mode, pin p1a is continuously active and pin p1d is modulated. in the reverse mode, pin p1c is continuously active and pin p1b is modulated. these are illustrated in figure 17-6. p1a, p1b, p1c and p1d outputs are multiplexed with the portc<2>, porte<6:5> and portg<4> data latches. the trisc<2>, trisc<6:5> and trisg<4> bits must be cleared to make the p1a, p1b, p1c and p1d pins outputs. figure 17-6: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. note 2: output signal is shown as active-high.
PIC18F6525/6621/8525/8621 ds39612b-page 166 ? 2005 microchip technology inc. figure 17-7: example of full-bridge application 17.4.5.1 direction change in full-bridge mode in the full-bridge output mode, the p1m1 bit in the ccp1con register allows users to control the forward/ reverse direction. when the application firmware changes this direction control bit, the module will assume the new direction on the next pwm cycle. just before the end of the current pwm period, the modulated outputs (p1b and p1d) are placed in their inactive state, while the unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. this occurs in a time interval of (4 t osc * (timer2 prescale value) before the next pwm period begins. the timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the t2ckps bit (t2con<1:0>). during the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (p1b and p1d) remain inactive. this relationship is shown in figure 17-8. note that in the full-bridge output mode, the eccp1 module does not provide any dead-band delay. in gen- eral, since only one output is modulated at all times, dead-band delay is not required. however, there is a situation where a dead-band delay might be required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. figure 17-9 shows an example where the pwm direction changes from forward to reverse at a near 100% duty cycle. at time t1, the output p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices qc and qd (see figure 17-7) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. reduce pwm for a pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. pic18f6x2x/8x2x p1a p1c fet driver fet driver v+ v- load fet driver fet driver p1b p1d qa qb qd qc
? 2005 microchip technology inc. ds39612b-page 167 PIC18F6525/6621/8525/8621 figure 17-8: pwm direction change figure 17-9: pwm direction chang e at near 100% duty cycle dc period (1) signal note 1: the direction bit in the eccp1 control register (ccp 1con<7>) is written any time during the pwm cycle. 2: when changing directions, the p1a and p1c signals switch before the end of the current pwm cycle at intervals of 4 t osc , 16 t osc or 64 t osc , depending on the timer2 prescaler value. the modulated p1b and p1d signals are inactive at this time. period (note 2) p1a (active-high) p1b (active-high) p1c (active-high) p1d (active-high) dc forward period reverse period p1a (1) t on (2) t off (3) t = t off ? t on (2,3) p1b (1) p1c (1) p1d (1) external switch d (1) potential shoot-through current (1) note 1: all signals are shown as active-high. 2: t on is the turn-on delay of power switch qc and its driver. 3: t off is the turn-off delay of power switch qd and its driver. external switch c (1) t1 dc dc
PIC18F6525/6621/8525/8621 ds39612b-page 168 ? 2005 microchip technology inc. 17.4.6 programmable dead-band delay in half-bridge applications where all power switches are modulated at the pwm frequency at all times, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) may flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flow- ing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally program- mable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 17-4 for illustration. the lower seven bits of the eccpxdel register (register 17-2) set the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). 17.4.7 enhanced pwm auto-shutdown when an eccp module is programmed for any pwm mode, the active output pin(s) may be configured for auto-shutdown. auto-shutdown immediately places the pwm output pin(s) into a defined shutdown state when a shutdown event occurs. a shutdown event can be caused by either of the two comparator modules or the int0/flt0 pin (or any com- bination of these three sour ces). the comparators may be used to monitor a voltage input proportional to a cur- rent being monitored in the bridge circuit. if the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. alternatively, a digital signal on the int0/flt0 pin can also trigger a shutdown. the auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. the auto-shutdown sources to be used are selected using the eccp1as2:eccp1as0 bits (bits<6:4> of the eccp1as register). when a shutdown occurs, the output pin(s) are asynchronously placed in their shutdown states, specified by the pss1ac1:pss1ac0 and pss1bd1:pss1bd0 bits (eccp1as3:eccp1as0). each pin pair (p1a/p1c and p1b/p1d) may be set to drive high, drive low or be tri-stated (not driving). the eccp1ase bit (eccp1as<7>) is also set to hold the enhanced pwm outputs in their shutdown states. the eccp1ase bit is set by hardware when a shutdown event occurs. if automatic restarts are not enabled, the eccpase bit is cleared by firmware when the cause of the shutdown clears. if automatic restarts are enabled, the eccpase bit is automatically cleared when the cause of the auto-shutdown has cleared. if the eccpase bit is set when a pwm period begins, the pwm outputs remain in their shutdown state for that entire pwm period. when the eccpase bit is cleared, the pwm outputs will return to normal operation at the beginning of the next pwm period. register 17-2: eccpxdel: pwm configuratio n register note: writing to the eccpase bit is disabled while a shutdown condition is active. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxrsen pxdc6 pxdc5 pxdc 4 pxdc3 pxdc2 pxdc1 pxdc0 bit 7 bit 0 bit 7 pxrsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpxase bit cl ears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpxase must be cleared in software to restart the pwm bit 6-0 pxdc6:pxdc0: pwm delay count bits delay time, in number of f osc /4 (4 * t osc ) cycles, between the scheduled and actual time for a pwm signal to transition to active. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 169 PIC18F6525/6621/8525/8621 register 17-3: eccpxas: enhanced capture/compare/pwm auto-shutdown control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpxase eccpxas2 eccpxas1 eccpxas0 pssxac1 pssxac0 pssxbd1 pssxbd0 bit 7 bit 0 bit 7 eccpxase: eccp auto-shutdown event status bit 0 = eccp outputs are operating 1 = a shutdown event has occurred; eccp outputs are in shutdown state bit 6-4 eccpxas2:eccpxas0: eccp auto-shutdown source select bits 000 = auto-shutdown is disabled 001 = comparator 1 output 010 = comparator 2 output 011 = either comparator 1 or 2 100 = int0/flt0 101 = int0/flt0 or comparator 1 110 = int0/flt0 or comparator 2 111 = int0/flt0 or comparator 1 or comparator 2 bit 3-2 pssxac1:pssxac0: pins a and c shutdown state control bits 00 = drive pins a and c to ? 0 ? 01 = drive pins a and c to ? 1 ? 1x = pins a and c tri-state bit 1-0 pssxbd1:pssxbd0: pins b and d shutdown state control bits 00 = drive pins b and d to ? 0 ? 01 = drive pins b and d to ? 1 ? 1x = pins b and d tri-state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 170 ? 2005 microchip technology inc. 17.4.7.1 auto-shutdown and automatic restart the auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. this is enabled by setting the p1rsen bit of the eccp1del register (eccp1del<7>). in shutdown mode with prsen = 1 (figure 17-10), the eccpase bit will remain set for as long as the cause of the shutdown continues. when the shutdown condi- tion clears, the eccp1ase bit is cleared. if prsen = 0 (figure 17-11), once a shutdown condition occurs, the eccp1ase bit will remain set until it is cleared by firmware. once eccp1ase is cleared, the enhanced pwm will resume at the beginning of the next pwm period. independent of the p1rsen bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. the eccp1ase bit can- not be cleared as long as the cause of the shutdown persists. the auto-shutdown mode can be forced by writing a ? 1 ? to the eccpase bit. 17.4.8 start-up considerations when the eccp module is used in the pwm mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. when the microcontroller is released from reset, all of the i/o pins are in the high-impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels, or activates the pwm output(s). the ccp1m1:ccp1m0 bits (ccp1con<1:0>) allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polarities must be selected before the pwm pins are configured as outputs. changing the polarity configura- tion while the pwm pins are configured as outputs is not recommended since it may result in damage to the application circuits. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the eccp module may cause damage to the applica- tion circuit. the eccp module must be enabled in the proper output mode and complete a full pwm cycle before configuring the pwm pins as outputs. the com- pletion of a full pwm cycle is indicated by the tmr2if bit being set as the second pwm period begins. figure 17-10: pwm auto-shutdown (prsen = 1 , auto-restart enabled) figure 17-11: pwm auto-shutdown (prsen = 0 , auto-restart disabled) note: writing to the eccpase bit is disabled while a shutdown condition is active. shutdown pwm eccpase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period pwm period shutdown pwm eccpase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period eccpase cleared by firmware pwm period
? 2005 microchip technology inc. ds39612b-page 171 PIC18F6525/6621/8525/8621 17.4.9 setup for pwm operation the following steps should be taken when configuring the eccp1 module for pwm operation using timer2: 1. configure the pwm pins, p1a and p1b (and p1c and p1d, if used), as inputs by setting the corresponding tris bits. 2. set the pwm period by loading the pr2 register. 3. if auto-shutdown is required do the following: disable auto-shutdown (eccp1as = 0 ) configure source (flt0, comparator 1 or comparator 2) wait for non-shutdown condition 4. configure the eccp1 module for the desired pwm mode and configuration by loading the ccp1con register with the appropriate values: select one of the available output configurations and direction with the p1m1:p1m0 bits. select the polarities of the pwm output signals with the ccp1m3:ccp1m0 bits. 5. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 6. for half-bridge output mode, set the dead-band delay by loading eccp1del<6:0> with the appropriate value. 7. if auto-shutdown operation is required, load the eccp1as register: select the auto-shutdown sources using the eccp1as2:eccp1as0 bits. select the shutdown states of the pwm output pins using the pss1ac1:pss1ac0 and pss1bd1:pss1bd0 bits. set the eccp1ase bit (eccp1as<7>). configure the comparators using the cmcon register. configure the comparator inputs as analog inputs. 8. if auto-restart operation is required, set the p1rsen bit (eccp1del<7>). 9. configure and start tmr2: clear the tmr2 interrupt flag bit by clearing the tmr2if bit (pir1<1>). set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). enable timer2 by setting the tmr2on bit (t2con<2>). 10. enable pwm outputs after a new pwm cycle has started: wait until tmrn overflows (tmrnif bit is set). enable the eccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective tris bits. clear the eccp1ase bit (eccp1as<7>). 17.4.10 effects of a reset both power-on reset and subsequent resets will force all ports to input mode and the ccp registers to their reset states. this forces the enhanced ccp module to reset to a state compatible with the standard ccp module.
PIC18F6525/6621/8525/8621 ds39612b-page 172 ? 2005 microchip technology inc. table 17-5: registers associated with eccp modules and timer1 to timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ? ? ri to pd por bor 0--1 11qq 0--q qquu pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ietmr2ietmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1iptmr2iptmr1ip 1111 1111 1111 1111 pir2 ? cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 ---0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 ---0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 ---1 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 trisb portb data direction register 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 triscd portd data direction register 1111 1111 1111 1111 trise porte data direction register 1111 1111 1111 1111 trisf portf data direction register 1111 1111 1111 1111 trisg ? ? ? portg data direction register ---1 1111 ---1 1111 trish porth data direction register 1111 1111 1111 1111 tmr1l timer1 register low byte xxxx xxxx uuuu uuuu tmr1h timer1 register high byte xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu tmr2 timer2 register 0000 0000 0000 0000 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 tmr3l timer3 register low byte xxxx xxxx uuuu uuuu tmr3h timer3 register high byte xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu tmr4 timer4 register 0000 0000 0000 0000 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 -000 0000 pr4 timer4 period register 1111 1111 1111 1111 ccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 eccp1as eccp1ase eccp1as2 eccp1as1 eccp1as0 pss1ac1 pss1ac0 pss1bd1 pss1bd0 0000 0000 0000 0000 eccp1del p1rsen p1dc6 p1dc5 p1dc4 p1dc3 p1dc2 p1dc1 p1dc0 0000 0000 uuuu uuuu ccpr2l enhanced capture/compare/pwm register 2 low byte xxxx xxxx uuuu uuuu ccpr2h enhanced capture/compare/pwm register 2 high byte xxxx xxxx uuuu uuuu ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 0000 0000 eccp2as eccp2ase eccp2as2 eccp2as1 eccp2as0 pss2ac1 pss2ac0 pss2bd1 pss2bd0 0000 0000 0000 0000 eccp2del p2rsen p2dc6 p2dc5 p2dc4 p2dc3 p2dc2 p2dc1 p2dc0 0000 0000 uuuu uuuu ccpr3l enhanced capture/compare/pwm register 3 low byte xxxx xxxx uuuu uuuu ccpr3h enhanced capture/compare/pwm register 3 high byte xxxx xxxx uuuu uuuu ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 0000 0000 eccp3as eccp3ase eccp3as2 eccp3as1 eccp3as0 pss3ac1 pss3ac0 pss3bd1 pss3bd0 0000 0000 0000 0000 eccp3del px3rsen p3dc6 p3dc5 p3dc4 p3dc3 p3dc2 p3dc1 p3dc0 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used during eccp operation. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 173 PIC18F6525/6621/8525/8621 18.0 master synchronous serial port (mssp) module 18.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 18.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual configuration bits differ significantly depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 18.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) ? rc5/sdo serial data in (sdi) ? rc4/sdi/sda serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ? rf7/ss figure 18-1 shows the block diagram of the mssp module when operating in spi mode. figure 18-1: mssp block diagram (spi? mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to txx/rxx in sspsr tris bit 2 smp:cke rc5/sdo sspbuf reg rc4/sdi/sda rf7/ss rc3/sck/ scl
PIC18F6525/6621/8525/8621 ds39612b-page 174 ? 2005 microchip technology inc. 18.3.1 registers the mssp module has four registers for spi mode operation. these are: mssp control register 1 (sspcon1) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 regis- ter is readable and writable. the lower 6 bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 18-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock edge select bit 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state note: polarity of clock state is set by the ckp bit (sspcon1<4>). bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write bit information used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 175 PIC18F6525/6621/8525/8621 register 18-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow note: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: master synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: master synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 176 ? 2005 microchip technology inc. 18.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0>) and sspstat<7:6>. these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>) and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 18-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 18-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2005 microchip technology inc. ds39612b-page 177 PIC18F6525/6621/8525/8621 18.3.3 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, re-initialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisf<7> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 18.3.4 typical connection figure 18-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? slave sends dummy data master sends data ? slave sends data master sends dummy data ? slave sends data figure 18-2: spi? master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi? master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi? slave sspm3:sspm0 = 010xb serial clock
PIC18F6525/6621/8525/8621 ds39612b-page 178 ? 2005 microchip technology inc. 18.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 18-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon1<4>). this then, would give waveforms for spi communication as shown in figure 18-3, figure 18-5 and figure 18-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 18-3 shows the waveforms for master mode. figure 18-3: spi? mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0
? 2005 microchip technology inc. ds39612b-page 179 PIC18F6525/6621/8525/8621 18.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit (sspcon1<4>). while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 18.3.7 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 18-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2
PIC18F6525/6621/8525/8621 ds39612b-page 180 ? 2005 microchip technology inc. figure 18-5: spi? mode waveform (slave mode with cke = 0 ) figure 18-6: spi? mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 bit 0 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2 bit 7
? 2005 microchip technology inc. ds39612b-page 181 PIC18F6525/6621/8525/8621 18.3.8 sleep operation in master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device from sleep. 18.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 18.3.10 bus mode compatibility table 18-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 18-1: spi? bus modes there is also a smp bit which controls when the data is sampled. table 18-2: registers associated with spi? operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 sspbuf mssp receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi? mode. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 182 ? 2005 microchip technology inc. 18.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) ? rc3/sck/scl serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs or outputs through the trisc<4:3> bits. figure 18-7: mssp block diagram (i 2 c? mode) 18.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register 1 (sspcon1) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read- only. the upper two bits of the sspstat are read/ write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the mssp is configured in i 2 c slave mode. when the mssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
? 2005 microchip technology inc. ds39612b-page 183 PIC18F6525/6621/8525/8621 register 18-3: sspstat: mssp status register (i 2 c mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset and when sspen is cleared. bit 2 r/w : read/write bit information (i 2 c mode only) in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = sspbuf is full 0 = sspbuf is empty in receive mode: 1 = sspbuf is full (does not include the ack and stop bits) 0 = sspbuf is empty (does not include the ack and stop bits) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 184 ? 2005 microchip technology inc. register 18-4: sspcon1: mssp control register 1 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: master synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, the sda and scl pins must be properly configured as input or output. bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: master synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note: bit combinations not specifically listed here are either reserved or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 185 PIC18F6525/6621/8525/8621 register 18-5: sspcon2: mssp control register 2 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 186 ? 2005 microchip technology inc. 18.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon<5>). the sspcon1 register allows control of the i 2 c oper- ation. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = (f osc /4) x (sspadd + 1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled i 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 18.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit bf (sspstat<0>) was set before the transfer was received. the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter 100 and parameter 101. 18.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit bf is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated, if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif.
? 2005 microchip technology inc. ds39612b-page 187 PIC18F6525/6621/8525/8621 18.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set, or bit sspov (sspcon1<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit, sspif (pir1<3>), must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon1<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit ckp (sspcon<4>). see section 18.4.4 ?clock stretching? for more detail. 18.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regardless of sen (see section 18.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then pin rc3/ sck/scl should be enabled by setting bit, ckp (sspcon1<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 18-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse.
PIC18F6525/6621/8525/8621 ds39612b-page 188 ? 2005 microchip technology inc. figure 18-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 2 34 56 7 8 91 234 5 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 )
? 2005 microchip technology inc. ds39612b-page 189 PIC18F6525/6621/8525/8621 figure 18-9: i 2 c? slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software scl held low while cpu responds to sspif
PIC18F6525/6621/8525/8621 ds39612b-page 190 ? 2005 microchip technology inc. figure 18-10: i 2 c? slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place
? 2005 microchip technology inc. ds39612b-page 191 PIC18F6525/6621/8525/8621 figure 18-11: i 2 c? slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 1234 5 6789 12345678 9 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bf flag is clear third address sequence at the end of the
PIC18F6525/6621/8525/8621 ds39612b-page 192 ? 2005 microchip technology inc. 18.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 18.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence if the bf bit is set, the ckp bit in the sspcon1 register is automatically cleared, forcing the scl output to be held low. the ckp being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 18-13). 18.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 18.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 18-9). 18.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high- order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 18-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
? 2005 microchip technology inc. ds39612b-page 193 PIC18F6525/6621/8525/8621 18.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to ? 0 ?. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 18-12). figure 18-12: clock synchronization timing sda scl dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock
PIC18F6525/6621/8525/8621 ds39612b-page 194 ? 2005 microchip technology inc. figure 18-13: i 2 c? slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 56 7 8 9 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ?0? and clock stretching occurs
? 2005 microchip technology inc. ds39612b-page 195 PIC18F6525/6621/8525/8621 figure 18-14: i 2 c? slave mode timing sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 567 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6 a5 a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
PIC18F6525/6621/8525/8621 ds39612b-page 196 ? 2005 microchip technology inc. 18.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 18-15). figure 18-15: slave mode general call address sequence (7-bit or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt ? 0 ? ? 1 ?
? 2005 microchip technology inc. ds39612b-page 197 PIC18F6525/6621/8525/8621 18.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code con- ducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause mssp interrupt flag bit, sspif, to be set (mssp interrupt, if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 18-16: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, start bit detect sspbuf internal data bus set/reset s, p, wcol (sspstat), shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif, reset ackstat, pen (sspcon2) rate generator sspm3:sspm0
PIC18F6525/6621/8525/8621 ds39612b-page 198 ? 2005 microchip technology inc. 18.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode oper- ation is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 18.4.7 ?baud rate generator? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out of the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out of the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete.
? 2005 microchip technology inc. ds39612b-page 199 PIC18F6525/6621/8525/8621 18.4.7 baud rate generator in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 18-17). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to ? 0 ? and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 18-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. figure 18-17: baud rate generator block diagram table 18-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f osc f cy f cy *2 brg value f scl (2 rollovers of brg) 40 mhz 10 mhz 20 mhz 18h 400 khz (1) 40 mhz 10 mhz 20 mhz 1fh 312.5 khz 40 mhz 10 mhz 20 mhz 63h 100 khz 16 mhz 4 mhz 8 mhz 09h 400 khz (1) 16 mhz 4 mhz 8 mhz 0ch 308 khz 16 mhz 4 mhz 8 mhz 27h 100 khz 4 mhz 1 mhz 2 mhz 02h 333 khz (1) 4 mhz 1 mhz 2 mhz 09h 100 khz 4 mhz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application.
PIC18F6525/6621/8525/8621 ds39612b-page 200 ? 2005 microchip technology inc. 18.4.7.1 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 18-18). figure 18-18: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 2005 microchip technology inc. ds39612b-page 201 PIC18F6525/6621/8525/8621 18.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 18.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 18-19: first start bit timing note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
PIC18F6525/6621/8525/8621 ds39612b-page 202 ? 2005 microchip technology inc. 18.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 18.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 18-20: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low-to-high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here rsen bit set by hardware on the falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change). scl = 1 occurs here. t brg t brg t brg and sets sspif
? 2005 microchip technology inc. ds39612b-page 203 PIC18F6525/6621/8525/8621 18.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 18-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 18.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 18.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 18.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 18.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/ low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 18.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 18.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 18.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
PIC18F6525/6621/8525/8621 ds39612b-page 204 ? 2005 microchip technology inc. figure 18-21: i 2 c? master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from mssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen r/w cleared in software
? 2005 microchip technology inc. ds39612b-page 205 PIC18F6525/6621/8525/8621 figure 18-22: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0 sspov is set because sspbuf is still full last bit is shifted into sspsr and contents are unloaded into sspbuf
PIC18F6525/6621/8525/8621 ds39612b-page 206 ? 2005 microchip technology inc. 18.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 18-23). 18.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 18.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sam- pled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 18-24). 18.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 18-23: acknowledge sequence waveform figure 18-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl sspif set at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 2005 microchip technology inc. ds39612b-page 207 PIC18F6525/6621/8525/8621 18.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 18.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 18.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the mssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 18.4.17 multi-master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state (figure 18-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 18-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0
PIC18F6525/6621/8525/8621 ds39612b-page 208 ? 2005 microchip technology inc. 18.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 18-26). b) scl is sampled low before sda is asserted low (figure 18-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted, the bclif flag is set and the mssp module is reset to its idle state (figure 18-26). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to ? 0 ?. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 18-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to ? 0 ? and during this time, if the scl pin is sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 18-26: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif.
? 2005 microchip technology inc. ds39612b-page 209 PIC18F6525/6621/8525/8621 figure 18-27: bus collision d uring start condition (scl = 0 ) figure 18-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s set sen, enable start sequence if sda = 1 , scl = 1 less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda.
PIC18F6525/6621/8525/8621 ds39612b-page 210 ? 2005 microchip technology inc. 18.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to ? 0 ?. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 18-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 18-30. if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 18-29: bus collision during a repeat ed start condition (case 1) figure 18-30: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
? 2005 microchip technology inc. ds39612b-page 211 PIC18F6525/6621/8525/8621 18.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to ? 0 ?. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 18-31). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 18-32). figure 18-31: bus collision during a stop condition (case 1) figure 18-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
PIC18F6525/6621/8525/8621 ds39612b-page 212 ? 2005 microchip technology inc. table 18-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 sspbuf mssp receive buffer/transmit register xxxx xxxx uuuu uuuu sspadd mssp address register in i 2 c slave mode. mssp baud rate reload register in i 2 c master mode. 0000 0000 0000 0000 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in i 2 c? mode. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 213 PIC18F6525/6621/8525/8621 19.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is one of the two serial i/o modules. (usart is also known as a serial communications interface or sci.) the eusart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the enhanced usart module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on sync break recep- tion and 12-bit break character transmit. these make it ideally suited for use in local interconnect network bus (lin bus) systems. the eusart can be configured in the following modes: asynchronous (full duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission synchronous ? master (half duplex) with selectable clock polarity synchronous ? slave (half duplex) with selectable clock polarity the pins of usart1 and usart2 are multiplexed with the functions of portc (rc6/tx1/ck1 and rc7/rx1/ dt1) and portg (rg1/tx2/ck2 and rg2/rx2/dt2), respectively. in order to configure these pins as an eusart: for usart1: - bit spen (rcsta1<7>) must be set (= 1 ) - bit trisc<7> must be set (= 1 ) - bit trisc<6> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode for usart2: - bit spen (rcsta2<7>) must be set (= 1 ) - bit trisg<2> must be set (= 1 ) - bit trisg<1> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode the operation of each enhanced usart module is controlled through three registers: transmit status and control (txstax) receive status and control (rcstax) baud rate control (baudconx) these are detailed on the following pages in register 19-1, register 19-2 and register 19-3, respectively. note: the eusart control will automatically reconfigure the pin from input to output as needed. note: throughout this section, references to register and bit names that may be associ- ated with a specific eusart module are referred to generically by the use of ?x? in place of the specific module number. thus, ?rcstax? might refer to the receive status register for either usart1 or usart2
PIC18F6525/6621/8525/8621 ds39612b-page 214 ? 2005 microchip technology inc. register 19-1: txstax: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync sendb brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: don?t care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 215 PIC18F6525/6621/8525/8621 register 19-2: rcstax: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rxx/dtx and txx/ckx pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcregx register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 216 ? 2005 microchip technology inc. register 19-3: baudconx: baud rate control register u-0 r-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ? rcidl ? sckp brg16 ? wue abden bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 rcidl : receive operation idle status bit 1 = receive operation is idle 0 = receive operation is active bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode: unused in this mode. synchronous mode: 1 = idle state for clock (ckx) is a high level 0 = idle state for clock (ckx) is a low level bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator ? spbrghx and spbrgx 0 = 8-bit baud rate generator ? spbrgx only (compatible mode), spbrghx value ignored bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusart will continue to sample the rxx pin ? interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rxx pin not monitored or rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud rate detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h); cleared in hardware upon completion 0 = baud rate measurement disabled or completed synchronous mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2005 microchip technology inc. ds39612b-page 217 PIC18F6525/6621/8525/8621 19.1 eusart baud rate generator (brg) the brg is a dedicated 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudconx<3>) selects 16-bit mode. the spbrghx:spbrgx register pair controls the period of a free running timer. in asynchronous mode, bits brgh (txstax<2>) and brg16 also control the baud rate. in synchronous mode, bit brgh is ignored. table 19-1 shows the formula for computation of the baud rate for different eusart modes which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrghx:spbrgx registers can be calculated using the formulas in table 19-1. from this, the error in baud rate can be determined. an example calculation is shown in example 19-1. typical baud rates and error values for the various asynchro- nous modes are shown in table 19-2. it may be advantageous to use the high baud rate (brgh = 1 ) or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrghx:spbrgx regis- ters causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 19.1.1 sampling the data on the rxx pin (either rc7/rx1/dt1 or rg2/ rx2/dt2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rxx pin. table 19-1: baud rate formulas example 19-1: calculating baud rate error table 19-2: registers associated with baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrghx:spbrgx register pair name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrghx:spbrgx] + 1)) solving for spbrghx:spbrgx: x = ((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? de sired baud rate)/desired baud rate = (9615 ? 9600)/9600 = 0.16%
PIC18F6525/6621/8525/8621 ds39612b-page 218 ? 2005 microchip technology inc. table 19-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ?
? 2005 microchip technology inc. ds39612b-page 219 PIC18F6525/6621/8525/8621 baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 ? ? ? 115.2 111.111 -3.55 8 ? ? ? ? ? ? table 19-3: baud rates for asynchronous modes (continued)
PIC18F6525/6621/8525/8621 ds39612b-page 220 ? 2005 microchip technology inc. 19.1.2 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 19-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rxx signal, the rxx signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value 55h (ascii ?u?, which is also the lin bus sync character), in order to calculate the proper bit rate. the measure- ment is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrgx begins counting up using the preselected clock source on the first rising edge of rxx. after eight bits on the rxx pin or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrghx:spbrgx register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. while calibrating the baud rate period, the brg regis- ters are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrgx and spbrghx will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrghx register. refer to table 19-4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rcxif interrupt is set once the fifth rising edge on rxx is detected. the value in the rcregx needs to be read to clear the rc1if interrupt. rcregx content should be discarded. table 19-4: brg counter clock rates figure 19-1: automatic baud rate calculation note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrgx and spbrghx are both used as a 16-bit counter, independent of brg16 setting. brg value rxx pin abden bit rcxif bit bit 0 bit 1 (interrupt) read rcregx brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrgx xxxxh 1ch spbrghx xxxxh 00h
? 2005 microchip technology inc. ds39612b-page 221 PIC18F6525/6621/8525/8621 19.2 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txstax<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusart module?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate depending on the brgh and brg16 bits (txstax<2> and baudconx<3>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the eusart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver auto-wake-up on sync break character 12-bit break character transmit auto-baud rate detection 19.2.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 19-2. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txregx register (if available). once the txregx register transfers the data to the tsr register (occurs in one t cy ), the txregx register is empty and flag bit txxif is set. this interrupt can be enabled/disabled by setting/clearing enable bit txxie. flag bit txxif will be set regardless of the state of enable bit txxie and cannot be cleared in software. flag bit txxif is not cleared immediately upon loading the transmit buffer register, txregx. txxif becomes valid in the second instruction cycle following the load instruc- tion. polling txxif immediately following a load of txregx will return invalid results. while flag bit txxif indicates the status of the txregx register, another bit, trmt (txstax<1>), shows the status of the tsr register. status bit trmt is a read-only bit which is set when the tsr register is empty. no inter- rupt logic is tied to this bit so the user has to poll this bit in order to determine if t he tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen which will also set bit txxif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txregx register (starts transmission). if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-2: eusart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit txxif is set when enable bit txen is set. txxif txxie interrupt txen baud rate clk spbrgx baud rate generator tx9d msb lsb data bus txregx register tsr register (8) 0 tx9 trmt spen txx pin pin buffer and control 8 ? ? ? spbrghx brg16
PIC18F6525/6621/8525/8621 ds39612b-page 222 ? 2005 microchip technology inc. figure 19-3: asynchronous transmission figure 19-4: asynchronous transmission (back to back) table 19-5: registers associated with asynchronous transmission word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txregx brg output (shift clock) txx txxif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy (pin) word 1 stop bit transmit shift reg. write to txregx brg output (shift clock) txx txxif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy (pin) start bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x txregx enhanced usartx transmit register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 223 PIC18F6525/6621/8525/8621 19.2.2 eusart asynchronous receiver the receiver block diagram is shown in figure 19-5. the data is received on the rxx pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcxie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcxif will be set when reception is complete and an interrupt will be generated if enable bit rcxie was set. 7. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcregx register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 19.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcxip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcxif bit will be set when reception is complete. the interrupt will be acknowledged if the rcxie and gie bits are set. 8. read the rcstax register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcregx to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 19-5: eusart receiv e block diagram x64 baud rate clk baud rate generator rxx pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcregx register fifo interrupt rcxif rcxie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrgx spbrghx brg16 or 4
PIC18F6525/6621/8525/8621 ds39612b-page 224 ? 2005 microchip technology inc. figure 19-6: asynchronous reception table 19-6: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rxx (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcregx rcxif (interrupt flag) oerr bit cren word 1 rcregx word 2 rcregx stop bit note: this timing diagram shows three words appearing on the rxx input. the rcregx (receive buffer register) is read after the third word causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcregx enhanced usartx receive register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 225 PIC18F6525/6621/8525/8621 19.2.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be performed. the auto-wake-up feature allows the con- troller to wake-up due to activity on the rxx/dtx line, while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudconx<1>). once set, the typical receive sequence on rxx/dtx is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rxx/dtx line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rc1if interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 19-7) and asynchronously, if the device is in sleep mode (figure 19-8). the interrupt condition is cleared by reading the rcregx register. the wue bit is automatically cleared once a low-to-high transition is observed on the rxx line following the wake-up event. at this point, the eusart module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 19.2.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rxx/dtx, information with any state changes before the stop bit may signal a false end-of- character and cause data or framing errors. to work properly, therefore, the init ial character in the trans- mission must be all ? 0 ?s. this can be 00h (8 bytes) for standard rs-232 devices, or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., xt or hs mode). the sync break (or wake-up signal) character must be of suffi- cient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 19.2.4.2 special considerations using the wue bit the timing of wue and rcxif events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an idle mode. the wake-up event causes a receive interrupt by setting the rcxif bit. the wue bit is cleared after this when a rising edge is seen on rxx/dtx. the interrupt condition is then cleared by reading the rcregx register. ordinarily, the data in rcregx will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rcxif flag is set should not be used as an indicator of the integrity of the data in rcregx. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. figure 19-7: auto-wake-up bit (wue) timings during normal operation figure 19-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rxx/dtx rcxif auto-cleared cleared due to user read of rcregx note: the eusart remains in idle while the wue bit is set. bit set by user line q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rxx/dtx rcxif cleared due to user read of rcregx sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends bit set by user note 1 auto-cleared line
PIC18F6525/6621/8525/8621 ds39612b-page 226 ? 2005 microchip technology inc. 19.2.5 break character sequence the enhanced usart module has the capability of sending the special break character sequences that are required by the lin bus standard. the break character transmit consists of a start bit, followed by twelve ? 0 ? bits and a stop bit. the frame break charac- ter is sent whenever the sendb and txen bits (txstax<3> and txstax<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txregx will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). note that the data value written to the txregx for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 19-9 for the timing of the break character sequence. 19.2.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txregx with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txregx to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txregx becomes empty, as indicated by the txxif, the next data byte can be written to txregx. 19.2.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 19.2.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusart will sample the next two transitions on rxx/ dtx, cause an rcxif interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abd bit once the txxif interrupt is observed. figure 19-9: send break character sequence write to txregx brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txxif bit (transmit buffer reg. empty flag) txx (pin) trmt bit (transmit shift reg. empty flag) sendb (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write
? 2005 microchip technology inc. ds39612b-page 227 PIC18F6525/6621/8525/8621 19.3 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txstax<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txstax<4>). in addition, enable bit spen (rcstax<7>) is set in order to configure the txx and rxx pins to ckx (clock) and dtx (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ckx line. clock polarity is selected with the sckp bit (baudconx<4>); setting sckp sets the idle state on ckx as high, while clearing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 19.3.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 19-2. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txregx (if available). once the txregx register transfers the data to the tsr register (occurs in one t cycle ), the txregx is empty and interrupt bit txxif is set. the interrupt can be enabled/disabled by setting/clearing enable bit txxie. flag bit txxif will be set regardless of the state of enable bit txxie and cannot be cleared in software. it will reset only when new data is loaded into the txregx register. while flag bit txxif indicates the status of the txregx register, another bit, trmt (txstax<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txregx register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-10: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx1/dt1 rc6/tx1/ck1 pin write to txreg1 reg tx1if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgx = 0 , continuous transmission of two 8-bit words. pin rc6/tx1/ck1 pin (sckp = 0 ) (sckp = 1 )
PIC18F6525/6621/8525/8621 ds39612b-page 228 ? 2005 microchip technology inc. figure 19-11: synchronous transmis sion (through txen) table 19-7: registers associated with synchronous master transmission rc7/rx1/dt1 pin rc6/tx1/ck1 pin write to txreg1 reg tx1if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x txregx enhanced usartx transmit register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 229 PIC18F6525/6621/8525/8621 19.3.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcstax<5>), or the continuous receive enable bit, cren (rcstax<4>). data is sampled on the rxx pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcxie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcxif will be set when reception is complete and an interrupt will be generated if the enable bit rcxie was set. 8. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcregx register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 19-12: synchronous reception (master mode, sren) cren bit rc7/rx1/dt1 rc7/tx1/ck1 pin write to bit sren sren bit rc1if bit (interrupt) read rxreg1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . rc7/tx1/ck1 pin pin (sckp = 0 ) (sckp = 1 )
PIC18F6525/6621/8525/8621 ds39612b-page 230 ? 2005 microchip technology inc. table 19-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ?rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcregx enhanced usartx receive register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ?rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 231 PIC18F6525/6621/8525/8621 19.4 eusart synchronous slave mode synchronous slave mode is entered by clearing bit csrc (txstax<7>). this mode differs from the syn- chronous master mode in that the shift clock is supplied externally at the ckx pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 19.4.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txregx and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txregx register. c) flag bit txxif will not be set. d) when the first word has been shifted out of tsr, the txregx register will transfer the second word to the tsr and flag bit txxif will now be set. e) if enable bit txxie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txxie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txregx register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 19-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x txregx enhanced usartx transmit register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
PIC18F6525/6621/8525/8621 ds39612b-page 232 ? 2005 microchip technology inc. 19.4.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcregx register; if the rc1ie enable bit is set, the interrupt generated will wake the chip from low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcxie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcxif will be set when reception is com- plete. an interrupt will be generated if enable bit rcxie was set. 6. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcregx register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 19-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir3 ? ? rc2if tx2if tmr4if ccp5if ccp4if ccp3if --00 0000 --00 0000 pie3 ? ? rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie --00 0000 --00 0000 ipr3 ? ? rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip --11 1111 --11 1111 rcstax spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x rcregx enhanced usartx receive register 0000 0000 0000 0000 txstax csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 baudconx ? rcidl ? sckp brg16 ? wue abden -1-0 0-00 -1-0 0-00 spbrghx enhanced usartx baud rate generator register high byte 0000 0000 0000 0000 spbrgx enhanced usartx baud rate generator register low byte 0000 0000 0000 0000 legend: x = unknown, ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices.
? 2005 microchip technology inc. ds39612b-page 233 PIC18F6525/6621/8525/8621 20.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for the PIC18F6525/6621 devices and 16 for the pic18f8525/8621 devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. a new feature for the a/d converter is the addition of programmable acquisition time. this feature allows the user to select a new channel for conversion and setting the go/done bit immediately. when the go/done bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. this removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see register 20-3 and section 20.5 ?a/d conversions? ). the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 20-1, controls the operation of the a/d module. the adcon1 register, shown in register 20-2, configures the functions of the port pins. the adcon2 register, shown in register 20-3, configures the a/d clock source, justification and auto-acquisition time. register 20-1: adcon0: a/d control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) (1) 1101 = channel 13 (an13) (1) 1110 = channel 14 (an14) (1) 1111 = channel 15 (an15) (1) note 1: these channels are not available on the PIC18F6525/6621 (64-pin) devices. bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress (setting this bit starts the a/d conversion which is automatically cleared by hardware when the a/d conversion is complete) 0 = a/d conversion not in progress bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 234 ? 2005 microchip technology inc. register 20-2: adcon1: a/d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 vcfg1:vcfg0: voltage reference configuration bits: bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown vcfg1 vcfg0 a/d v ref + a/d v ref - 00 av dd av ss 01 external v ref +av ss 10 av dd external v ref - 11 external v ref +external v ref - a = analog input d = digital i/o note: shaded cells indicate a/d channels available only on pic18f8525/8621 devices. pcfg3 pcfg0 an15 an14 an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a a a aaaaaaaaaaaaa 0001 d d a aaaaaaaaaaaaa 0010 d d d aaaaaaaaaaaaa 0011 d d d daaaaaaaaaaaa 0100 d d d ddaaaaaaaaaaa 0101 d d d dddaaaaaaaaaa 0110 d d d ddddaaaaaaaaa 0111 d d d ddddda a a aaaaa 1000 d d d ddddddaaaaaaa 1001 d d d dddddddaaaaaa 1010 d d d ddddddddaaaaa 1011 d d d dddddddddaaaa 1100 d d d ddddddddddaaa 1101 d d d dddddddddddaa 1110 d d d dddddddddddda 1111 d d d ddddddddddddd
? 2005 microchip technology inc. ds39612b-page 235 PIC18F6525/6621/8525/8621 register 20-3: adcon2: a/d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 000 = 0 t ad (1) 001 = 2 t ad 010 = 4 t ad 011 = 6 t ad 100 = 8 t ad 101 = 12 t ad 110 = 16 t ad 111 = 20 t ad bit 2-0 adcs2:adcs0: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (clock derived from a/d rc oscillator) (1) 100 = f osc /4 101 = f osc /16 110 = f osc /64 111 = f rc (clock derived from a/d rc oscillator) (1) note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 236 ? 2005 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/ v ref + pin and ra2/an2/v ref - pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. each port pin associated with the a/d converter can be configured as an analog input (ra3 can also be a voltage reference), or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 20-1. figure 20-1: a/d block diagram (input voltage) v ain v ref + reference voltage av dd vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 10-bit converter v ref - av ss a/d an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 1111 1110 1101 1100 1011 1010 1001 1000 note 1: channels an15 through an12 are not available on PIC18F6525/6621 devices. 2: i/o pins have diode protection to v dd and v ss .
? 2005 microchip technology inc. ds39612b-page 237 PIC18F6525/6621/8525/8621 the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/ adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 20.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (not required in case of auto-acquisition time). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 20-2: analog input model v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd 500 na legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance ss = sampling switch c hold = sample/hold capacitance (from dac) r ss = sampling switch resistance
PIC18F6525/6621/8525/8621 ds39612b-page 238 ? 2005 microchip technology inc. 20.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 20-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 20-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 20-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold = 120 pf rs = 2.5 k ? conversion error 1/2 lsb v dd =5v rss = 7 k ? temperature = 50 c (system max.) v hold = 0v @ time = 0 equation 20-1: acquisition time equation 20-2: a/d minimum charging time equation 20-3: calculating the minimum required acquisition time note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) (1 ? e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(120 pf)(1 k ? + r ss + r s ) ln(1/2047) t acq =t amp + t c + t coff temperature coefficient is only required for temperatures > 25 c. t acq =2 s + t c + [(temp ? 25 c)(0.05 s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004885) -120 pf (10.5 k ? ) ln(0.0004885) -1.26 s (-7.6241) 9.61 s t acq =2 s + 9.61 s + [(50 c ? 25 c)(0.05 s/ c)] 11.61 s + 1.25 s 12.86 s
? 2005 microchip technology inc. ds39612b-page 239 PIC18F6525/6621/8525/8621 20.2 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. it also gives users the option to use an automatically determined acquisition time. acquisition time may be set with the acqt2:acqt0 bits (adcon2<5:3>), which provides a range of 2 to 20 t ad . when the go/done bit is set, the a/d module continues to sample the input for the selected acquisi- tion time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. automatic acquisition is selected when the acqt2:acqt0 = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt2:acqt0 bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 20.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 20-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 20-1: t ad vs. device operating frequencies ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 PIC18F6525/6621/8525/8621 2 t osc 000 1.25 mhz 4 t osc 100 2.50 mhz 8 t osc 001 5.00 mhz 16 t osc 101 10.0 mhz 32 t osc 010 20.0 mhz 64 t osc 110 40.0 mhz rc x11 ?
PIC18F6525/6621/8525/8621 ds39612b-page 240 ? 2005 microchip technology inc. 20.4 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. 20.5 a/d conversions figure 20-3 shows the operation of the a/d converter after the godone bit has been set. clearing the go/ done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is aborted, a 2 t ad wait is required before the next acquisition is started. after this 2 t ad wait, acquisition on the selected channel is automatically started. figure 20-3: a/d conversion t ad cycles note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as a digital input will convert as an analog input. analog levels on a digitally configured input will not affect the conversion accuracy. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume current out of the device?s specification limits. note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 9 t ad 10 b1 b0 t cy - t ad next q4: adresh/adresl is loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0
? 2005 microchip technology inc. ds39612b-page 241 PIC18F6525/6621/8525/8621 20.6 use of the eccp2 trigger an a/d conversion can be started by the special event trigger of the eccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the go/done bit and starts a conversion. if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. table 20-2: summary of registers associated with a/d name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir2 ? cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 -0-0 0000 pie2 ? cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 -0-0 0000 ipr2 ? cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 -1-1 1111 adresh a/d result register high byte xxxx xxxx uuuu uuuu adresl a/d result register low byte xxxx xxxx uuuu uuuu adcon0 ? ? chs3 chs3 chs1 chs0 go/done adon --00 0000 --00 0000 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 0-00 0000 porta ? ra6 (2) ra5 ra4 ra3 ra2 ra1 ra0 -x0x 0000 -u0u 0000 trisa ?trisa6 (2) porta data direction register -111 1111 -111 1111 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 u000 0000 trisf portf data direction control register 1111 1111 1111 1111 porth (3) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 0000 xxxx 0000 uuuu trish (3) porth data direction control register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: enabled only in microcontroller mode for pic18f8525/8621 devices. 2: ra6 and associated bits are configured as port pins in rcio and ecio oscillator modes only and read ? 0 ? in all other oscillator modes. 3: implemented on pic18f8525/8621 devices only, otherwise read as ? 0 ?.
PIC18F6525/6621/8525/8621 ds39612b-page 242 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 243 PIC18F6525/6621/8525/8621 21.0 comparator module the comparator module contains two analog comparators. the inputs to the comparators are multiplexed with the rf1 through rf6 pins. the on- chip voltage reference ( section 22.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register, shown as register 21-1, con- trols the comparator input and output multiplexers. a block diagram of the various comparator configurations is shown in figure 21-1. register 21-1: cmcon: comp arator control register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rf5/an10 c2 v in - connects to rf3/an8 0 =c1 v in - connects to rf6/an11 c2 v in - connects to rf4/an9 bit 2-0 cm2:cm0 : comparator mode bits figure 21-1 shows the comparator modes and the cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 244 ? 2005 microchip technology inc. 21.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 21-1 shows the eight possible modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 27.0 ?electrical characteristics? . figure 21-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 rf6/an11 v in - v in + rf5/an10/ off (read as ? 0 ?) comparators reset (por default value) a a cm2:cm0 = 000 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ?) a a c1 rf6/an11 v in - v in + rf5/an10/ c1out two independent comparators a a cm2:cm0 = 010 c2 rf4/an9 v in - v in + rf3/an8 c2out a a c1 rf6/an11 v in - v in + rf5/an10/ c1out two common reference comparators a a cm2:cm0 = 100 c2 rf4/an9 v in - v in + rf3/an8 c2out a d c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 rf6/an11 v in - v in + rf5/an10/ c1out a a c1 rf6/an11 v in - v in + rf5/an10/ off (read as ? 0 ?) comparators off d d cm2:cm0 = 111 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ?) d d c1 rf6/an11 v in - v in + rf5/an10/ c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 rf4/an9 v in - v in + rf3/an8 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 rf6/an11 v in - v in + rf5/an10/ c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 rf4/an9 v in - v in + rf3/an8 c2out a d a = analog input, port reads zeros always d = digital i nput cis (cmcon<3>) is the comparator input switch cv ref c1 rf6/an11 v in - v in + rf5/an10/ c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 rf4/an9 v in - v in + rf3/an8 c2out a a rf2/an7/c1out rf1/an6/c2out rf2/an7/c1out rf1/an6/c2out rf2/an7/c1out cv ref cv ref cv ref cv ref cv ref cv ref cv ref cv ref
? 2005 microchip technology inc. ds39612b-page 245 PIC18F6525/6621/8525/8621 21.2 comparator operation a single comparator is shown in figure 21-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 21-2 represent the uncertainty due to input offsets and response time. 21.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 21-2). figure 21-2: single comparator 21.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 21.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 22.0 ?comparator voltage reference module? contains a detailed description of the comparator voltage refer ence module that provides this signal. the internal reference signal is used when comparators are in mode cm<2:0> = 110 (figure 21-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 21.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used ( section 27.0 ?electrical characteristics? ). 21.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexors in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 21-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
PIC18F6525/6621/8525/8621 ds39612b-page 246 ? 2005 microchip technology inc. figure 21-3: comparator output block diagram 21.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit must be reset by clearing ? 0 ?. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. d q en to rf1 or rf2 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon r eset from other comparator cxinv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2005 microchip technology inc. ds39612b-page 247 PIC18F6525/6621/8525/8621 21.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 21.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator reset mode, cm<2:0> = 000 . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered down during the reset interval. 21.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 21-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 21-4: comparator analog input model va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input
PIC18F6525/6621/8525/8621 ds39612b-page 248 ? 2005 microchip technology inc. table 21-1: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 0000 0000 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ?cmif ? eeif bclif lvdif tmr3if ccp2if -0-0 0000 -0-0 0000 pie2 ?cmie ? eeie bclie lvdie tmr3ie ccp2ie -0-0 0000 -0-0 0000 ipr2 ?cmip ? eeip bclip lvdip tmr3ip ccp2ip -1-1 1111 -1-1 1111 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 u000 0000 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx uuuu uuuu trisf trisf7 trisf6 trisf5 tris f4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module.
? 2005 microchip technology inc. ds39612b-page 249 PIC18F6525/6621/8525/8621 22.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the cvrcon register controls the operation of the reference as shown in register 22-1. the block diagram is given in figure 22-1. the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra3 and ra2. the comparator reference supply voltage is controlled by the cvrss bit. 22.1 configuring the comparator voltage reference the comparator voltage reference can output 16 distinct voltage levels for each range. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = (cvr<3:0>/24) x cv rsrc if cvrr = 0 : cv ref = (cv rsrc x 1/4) + (cvr<3:0>/32) x cv rsrc the settling time of the comparator voltage reference must be considered when changing the cv ref output ( section 27.0 ?electrical characteristics? ). register 22-1: cvrcon: comparator voltage reference control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 =cv ref voltage level is also output on the rf5/an10/cv ref pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref pin note 1: if enabled for output, rf5 must also be configured as an input by setting trisf<5> to ? 1 ?. bit 5 cvrr : comparator v ref range selection bit 1 =0.00 cv rsrc to 0.667 cv rsrc , with cv rsrc /24 step size (low range) 0 =0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size (high range) bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = v ref + ? v ref - 0 = comparator reference source, cv rsrc = av dd ? av ss bit 3-0 cvr3:cvr0: comparator v ref value selection bits (0 vr3:vr0 15) when cvrr = 1 : cv ref = (cvr<3:0>/ 24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr3:cvr0/32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 250 ? 2005 microchip technology inc. figure 22-1: comparator voltage refe rence block diagram 22.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 22-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 27.0 ?electrical characteristics? . 22.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 22.4 effects of a reset a device reset disables the voltage reference by clearing bit cvren (cvrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit cvroe (cvrcon<6>) and selects the high- voltage range by clearing bit cvrr (cvrcon<5>). the vrss value select bits, cvrcon<3:0>, are also cleared. 22.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the trisf<5> bit is set and the cvroe bit is set. enabling the voltage reference output onto the rf5 pin configured as a digital input will increase current consumption. connecting rf5 as a digital output with vrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to v ref . figure 22-2 shows an example buffering technique. note: r is defined in section 27.0 ?electrical characteristics? . cvrr 8r cvr3 cvr0 (from cvrcon<3:0>) 16-1 analog mux 8r r r r r cvren cv ref 16 stages cvrss = 0 av dd v ref + cvrss = 0 cvrss = 1 v ref - cvrss = 1
? 2005 microchip technology inc. ds39612b-page 251 PIC18F6525/6621/8525/8621 figure 22-2: comparator voltage reference output buffer example table 22-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the voltage reference conf iguration bits, cvrcon<3:0> and cvrcon<5>. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 0000 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference.
PIC18F6525/6621/8525/8621 ds39612b-page 252 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 253 PIC18F6525/6621/8525/8621 23.0 low-voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do ?housekeeping tasks? before the device voltage exits the valid operating range. this can be done using the low-voltage detect module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low-voltage detect circuitry is completely under software control. this allows the circuitry to be ?turned off? by the software which minimizes the current consumption for the device. figure 23-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference t b ? t a is the total time for shutdown. figure 23-1: typical low-voltage detect application the block diagram for the lvd module is shown in figure 23-2. a comparator uses an internally gener- ated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a ?trip point? voltage. the ?trip point? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2v internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 23-2). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend:
PIC18F6525/6621/8525/8621 ds39612b-page 254 ? 2005 microchip technology inc. figure 23-2: low-voltage detect (lvd) block diagram the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits lvdl3:lvdl0 are set to ? 1111 ?. in this state, the com- parator input is multiplexed from the external input pin, lvdin (figure 23-3). this gives users flexibility because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 23-3: low-voltage detect (lvd) with external input block diagram lvdif v dd 16 to 1 mux lvden lvdcon internally generated reference voltage lvdin lvdl3:lvdl0 register lvd en 16 to 1 mux bgap boden lvden vxen lvdin v dd v dd externally generated trip point lvdl3:lvdl0 lvdcon register
? 2005 microchip technology inc. ds39612b-page 255 PIC18F6525/6621/8525/8621 23.1 control register the low-voltage detect control register (register 23-1) controls the operation of the low-voltage detect circuitry. register 23-1: lvdcon: low-voltag e detect control register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low-voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low-voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low-voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low-voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.45v-4.83v 1101 = 4.16v-4.5v 1100 = 3.96v-4.3v 1011 = 3.76v-3.92v 1010 = 3.57v-3.87v 1001 = 3.47v-3.75v 1000 = 3.27v-3.55v 0111 = 2.98v-3.22v 0110 = 2.77v-3.01v 0101 = 2.67v-2.89v 0100 = 2.48v-2.68v 0011 = 2.37v-2.57v 0010 = 2.18v-2.36v 0001 = 1.98v-2.14v 0000 = reserved note: lvdl3:lvdl0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 256 ? 2005 microchip technology inc. 23.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be constantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register) which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 23-4 shows typical waveforms that the lvd module may be used to detect. figure 23-4: low-voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated t irvst lvdif may not be set enable lvd lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable t irvst
? 2005 microchip technology inc. ds39612b-page 257 PIC18F6525/6621/8525/8621 23.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter 36. the low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 23-4. 23.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter d022b. 23.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake-up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 23.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off.
PIC18F6525/6621/8525/8621 ds39612b-page 258 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 259 PIC18F6525/6621/8525/8621 24.0 special features of the cpu there are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. these are: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming all PIC18F6525/6621/8525/8621 devices have a watchdog timer which is permanently enabled via the configuration bits, or software controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt) which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits is used to select various options. 24.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped, starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h through 3fffffh) which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the eecon1 register wr bit starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction, with the tblptr pointed to the configuration register, sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the configuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a ? 1 ? or a ? 0 ? into the cell. table 24-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ? ?oscsen ? fosc3 fosc2 fosc1 fosc0 --1- 1111 300002h config2l ? ? ? ? borv1 borv0 bor pwrten ---- 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten ---1 1111 300004h (1) config3l wait ? ? ? ? ?pm1pm0 1--- --11 300005h config3h mclre ? ? ? ? ?eccpmx (1) ccp2mx 1--- --11 300006h config4l debug ? ? ? ?lvp ?stvren 1--- -1-1 300008h config5l ? ? ? ?cp3 (2) cp2 cp1 cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ?wrt3 (2) wrt2 wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ?ebtr3 (2) ebtr2 ebtr1 ebtr0 ---- 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 (note 3) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 1010 legend: x = unknown, u = unchanged, ? = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: unimplemented in PIC18F6525/6621 devices; maintain this bit set. 2: unimplemented in pic18fx525 devices; maintain this bit set. 3: see register 24-13 for devid1 values.
PIC18F6525/6621/8525/8621 ds39612b-page 260 ? 2005 microchip technology inc. register 24-1: config1h: conf iguration register 1 high (byte address 300001h) u-0 u-0 r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? oscsen ? fosc3 fosc2 fosc1 fosc0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 oscsen : oscillator system clock switch enable bit 1 = oscillator system clock switch option is disabled (main oscillator is source) 0 = timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4 unimplemented: read as ? 0 ? bit 3-0 fosc3:fosc0 : oscillator selection bits 1111 = rc oscillator with osc2 configured as ra6 1110 = hs oscillator with sw enabled 4x pll 1101 = ec oscillator with osc2 configured as ra6 and sw enabled 4x pll 1100 = ec oscillator with osc2 configured as ra6 and hw enabled 4x pll 1011 = reserved; do not use 1010 = reserved; do not use 1001 = reserved; do not use 1000 = reserved; do not use 0111 = rc oscillator with osc2 configured as ra6 0110 = hs oscillator with hw enabled 4x pll 0101 = ec oscillator with osc2 configured as ra6 0100 = ec oscillator with osc2 configured as divide by 4 clock output 0011 = rc oscillator with osc2 configured as divide by 4 clock output 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2005 microchip technology inc. ds39612b-page 261 PIC18F6525/6621/8525/8621 register 24-2: config2l: configuration regi ster 2 low (byte address 300002h) register 24-3: config2h: co nfiguration register 2 high (byte address 300003h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? borv1 borv0 bor pwrten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-2 borv1:borv0: brown-out reset voltage bits 11 = v bor set to 2.0v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 1 bor: brown-out reset enable bit 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps2:wdtps0: watchdog timer postscaler select bits 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
PIC18F6525/6621/8525/8621 ds39612b-page 262 ? 2005 microchip technology inc. register 24-4: config3l: co nfiguration register 3 low (byte address 300004h) (1) register 24-5: config3h: co nfiguration register 3 high (byte address 300005h) r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 wait ? ? ? ? ?pm1pm0 bit 7 bit 0 bit 7 wait: external bus data wait enable bit 1 = wait selections unavailable for table reads and table writes 0 = wait selections for table reads and table writes are determined by wait1:wait0 bits (memcom<5:4>) bit 6-2 unimplemented: read as ? 0 ? bit 1-0 pm1:pm0: processor mode select bits 11 = microcontroller mode 10 = microprocessor mode 01 = microprocessor with boot block mode 00 = extended microcontroller mode note 1: this register is unimplemented for PIC18F6525/6621 devices; maintain these bits set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 mclre (1) ? ? ? ? ? eccpmx (2) ccp2mx bit 7 bit 0 bit 7 mclre: mclr enable bit (1) 1 = mclr pin enabled, rg5 input pin disabled 0 = rg5 input enabled, mclr disabled bit 6-2 unimplemented: read as ? 0 ? bit 1 eccpmx: eccp mux bit (2) 1 = eccp1 (p1b/p1c) and eccp3 (p3b/p3c) pwm outputs are multiplexed with re6 through re3 0 = eccp1 (p1b/p1c) and eccp3 (p3b/p3c) pwm outputs are multiplexed with rh7 through rh4 bit 0 ccp2mx: eccp2 mux bit in microcontroller mode: 1 = eccp2 input/output is multiplexed with rc1 0 = eccp2 input/output is multiplexed with re7 in microprocessor, microprocessor with boot block and extended microcontroller modes (pic18f8525/8621 devices only): 1 = eccp2 input/output is multiplexed with rc1 0 = eccp2 input/output is multiplexed with rb3 note 1: if mclr is disabled, either disable low-voltage icsp or hold rb5/kbi1/pgm low to ensure proper entry into icsp mode. 2: this register is unimplemented for PIC18F6525/6621 devices; maintain these bits set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2005 microchip technology inc. ds39612b-page 263 PIC18F6525/6621/8525/8621 register 24-6: config4l: configuration regi ster 4 low (byte address 300006h) register 24-7: config5l: configuration re gister 5 low (byte address 300008h) r/p-1 u-0 u-0 u-0 u-0 r/p-1 u-0 r/p-1 debug ? ? ? ?lvp ?stvren bit 7 bit 0 bit 7 debug : background debugger enable bit 1 = background debugger disabled. rb6 and rb7 configured as general purpose i/o pins. 0 = background debugger enabled. rb6 and rb7 are dedicated to in-circuit debug. bit 6-3 unimplemented: read as ? 0 ? bit 2 lvp: low-voltage icsp enable bit 1 = low-voltage icsp enabled 0 = low-voltage icsp disabled bit 1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?cp3 (1) cp2 cp1 cp0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 cp3: code protection bit (1) 1 = block 3 (00c000-00ffffh) not code-protected 0 = block 3 (00c000-00ffffh) code-protected note 1: unimplemented in pic18fx525 devices; maintain this bit set. bit 2 cp2: code protection bit 1 = block 2 (008000-00bfffh) not code-protected 0 = block 2 (008000-00bfffh) code-protected bit 1 cp1: code protection bit 1 = block 1 (004000-007fffh) not code-protected 0 = block 1 (004000-007fffh) code-protected bit 0 cp0: code protection bit 1 = block 0 (000800-003fffh) not code-protected 0 = block 0 (000800-003fffh) code-protected legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
PIC18F6525/6621/8525/8621 ds39612b-page 264 ? 2005 microchip technology inc. register 24-8: config5h: co nfiguration register 5 high (byte address 300009h) register 24-9: config6l: configuration regi ster 6 low (byte address 30000ah) r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb ? ? ? ? ? ? bit 7 bit 0 bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block (000000-0007ffh) not code-protected 0 = boot block (000000-0007ffh) code-protected bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?wrt3 (1) wrt2 wrt1 wrt0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 wrt3: write protection bit (1) 1 = block 3 (00c000-00ffffh) not write-protected 0 = block 3 (00c000-00ffffh) write-protected note 1: unimplemented in pic18fx525 devices; maintain this bit set. bit 2 wrt2: write protection bit 1 = block 2 (008000-00bfffh) not write-protected 0 = block 2 (008000-00bfffh) write-protected bit 1 wrt1: write protection bit 1 = block 1 (004000-007fffh) not write-protected 0 = block 1 (004000-007fffh) write-protected bit 0 wr0: write protection bit 1 = block 0 (000800-003fffh) not write-protected 0 = block 0 (000800-003fffh) write-protected legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2005 microchip technology inc. ds39612b-page 265 PIC18F6525/6621/8525/8621 register 24-10: config6h: configuration register 6 high (byte address 30000bh) register 24-11: config7l: configuration re gister 7 low (byte address 30000ch) r/c-1 r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc ? ? ? ? ? bit 7 bit 0 bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block (000000-0007ffh) not write-protected 0 = boot block (000000-0007ffh) write-protected bit 5 wrtc: configuration register write protection bit 1 = configuration registers (300000-3000ffh) not write-protected 0 = configuration registers (300000-3000ffh) write-protected bit 4-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ? ebtr3 (1) ebtr2 ebtr1 ebtr0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 ebtr3: table read protection bit (1) 1 = block 3 (00c000-00ffffh) not protected from table reads executed in other blocks 0 = block 3 (00c000-00ffffh) protected from table reads executed in other blocks note 1: unimplemented in pic18fx525 devices; maintain this bit set. bit 2 ebtr2: table read protection bit 1 = block 2 (008000-00bfffh) not protected from table reads executed in other blocks 0 = block 2 (008000-00bfffh) protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit 1 = block 1 (004000-007fffh) not protected from table reads executed in other blocks 0 = block 1 (004000-007fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit 1 = block 0 (000800-003fffh) not protected from table reads executed in other blocks 0 = block 0 (000800-003fffh) protected from table reads executed in other blocks legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
PIC18F6525/6621/8525/8621 ds39612b-page 266 ? 2005 microchip technology inc. register 24-12: config7h: configuration register 7 high (byte address 30000dh) register 24-13: devid1: device id register 1 for PIC18F6525/6621/8525/8621 devices (address 3ffffeh) register 24-14: devid2: device id register 2 for PIC18F6525/6621/8525/8621 devices (address 3fffffh) u-0 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 ? ebtrb ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 ebtrb: boot block table read protection bit 1 = boot block (000000-0007ffh) not protected from table reads executed in other blocks 0 = boot block (000000-0007ffh) protected from table reads executed in other blocks bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0: device id bits 100 = pic18f8621 101 = pic18f6621 110 = pic18f8525 111 = PIC18F6525 bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state r-0 r-0 r-0 r-0 r-1 r-0 r-1 r-0 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3: device id bits these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number. 0000 1010 = PIC18F6525/6621/8525/8621 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2005 microchip technology inc. ds39612b-page 267 PIC18F6525/6621/8525/8621 24.2 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clki pin. that means that the wdt will run even if the clock on the osc1/clki and osc2/clko/ra6 pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. the watchdog timer is enabled or disabled by a device configuration bit, wdten (config2h<0>). if wdten is set, software execution may not disable this function. when wdten is cleared, the swdten bit enables or disables the operation of the wdt. the wdt time-out period values may be found in the electrical specifications section under parameter 31. values for the wdt postscaler may be assigned using the configuration bits. 24.2.1 control register register 24-15 shows the wdtcon register. this is a readable and writable register which contains a control bit that allows software to override the wdt enable configuration bit only when the configuration bit has disabled the wdt. register 24-15: wdtcon: watchdog timer control register note 1: the clrwdt and sleep instructions clear the wdt and the postscaler if assigned to the wdt and prevent it from timing out and generating a device reset condition. 2: when a clrwdt instruction is executed and the postscaler is assigned to the wdt, the postscaler count will be cleared but the postscaler assignment is not changed. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off (if config2h<0> = 0 ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC18F6525/6621/8525/8621 ds39612b-page 268 ? 2005 microchip technology inc. 24.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler is selected at the time of the device programming by the value written to the config2h configuration register. figure 24-1: watchdog timer block diagram table 24-2: summary of registers associated with the watchdog timer postscaler wdt timer wdten 16-to-1 mux wdtps3:wdtps0 wdt time-out 16 swdten bit configuration bit note: wdtps3:wdtps0 are bits in register config2h. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? wdtps3 wdtps2 wdtps2 wdtps0 wdten rcon ipen ? ? ri to pd por bor wdtcon ? ? ? ? ? ? ?swdten legend: shaded cells are not used by the watchdog timer.
? 2005 microchip technology inc. ds39612b-page 269 PIC18F6525/6621/8525/8621 24.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (rcon<3>) is cleared, the to (rcon<4>) bit is set and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low or high-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for low- est current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 24.3.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from intx pin, rb port change or a peripheral interrupt. the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. tmr3 interrupt. timer3 must be operating as an asynchronous counter. 4. ccp capture mode interrupt (capture will not occur). 5. mssp (start/stop) bit detect interrupt. 6. mssp transmit or receive in slave mode (spi/i 2 c). 7. usart rxx or txx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). 9. eeprom write operation complete. 10. lvd interrupt. other peripherals cannot generate interrupts since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a ?wake-up?. the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 24.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction.
PIC18F6525/6621/8525/8621 ds39612b-page 270 ? 2005 microchip technology inc. figure 24-2: wake-up from sleep through interrupt (1,2) 24.4 program verification and code protection the overall structure of the code protection on the pic18 flash devices differs significantly from other picmicro devices. the user program memory is divided on binary bound- aries into four blocks of 16 kbytes each. the first block is further divided into a boot block of 2048 bytes and a second block (block 0) of 14 kbytes. each of the blocks has three code protection bits associated with them. they are: code-protect bit (cpn) write-protect bit (wrtn) external block table read bit (ebtrn) figure 24-3 shows the program memory organization for 48 and 64-kbyte devices and the specific code protection bit associated with each block. the actual locations of the bits are summarized in table 24-3. figure 24-3: code-protected program memory for PIC18F6525/6621/8525/8621 devices q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gieh bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc + 2 pc + 4 inst(pc) = sleep inst(pc ? 1) inst(pc + 2) sleep processor in sleep interrupt latency (3) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost (2) pc + 4 note 1: xt, hs or lp oscillator mode assumed. 2: gie = 1 assumed. in this case, after wake-up, the pr ocessor jumps to the interrupt routine. if gie = 0 , execution will continue in-line. 3: t ost = 1024 t osc (drawing not to scale). this delay will not occur for rc and ec oscillator modes. 4: clko is not available in these oscillator modes but shown here for timing reference. memory size/device block code protection controlled by: 48 kbytes (pic18fx525) 64 kbytes (pic18fx621) address range boot block boot block 000000h 0007ffh cpb, wrtb, ebtrb block 0 block 0 000800h 003fffh cp0, wrt0, ebtr0 block 1 block 1 004000h 007fffh cp1, wrt1, ebtr1 block 2 block 2 008000h 00bfffh cp2, wrt2, ebtr2 unimplemented, read ? 0 ? block 3 00c000h 00ffffh cp3, wrt3, ebtr3
? 2005 microchip technology inc. ds39612b-page 271 PIC18F6525/6621/8525/8621 table 24-3: summary of registers associated with code protection 24.4.1 program memory code protection the user memory may be read to or written from any location using the table read and table write instruc- tions. the device id register may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in user mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is ? 0 ?. the ebtrn bits control table reads. for a block of user memory with the ebtrn bit set to ? 0 ?, a table read instruction that executes from within that block is allowed to read. a table read instruction that executes from a location out- side of that block is not allowed to read and will result in reading ? 0 ?s. figures 24-4 through 24-6 illustrate table write and table read protection. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l ? ? ? ?cp3 (1) cp2 cp1 cp0 300009h config5h cpd cpb ? ? ? ? ? ? 30000ah config6l ? ? ? ?wrt3 (1) wrt2 wrt1 wrt0 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 30000ch config7l ? ? ? ? ebtr3 (1) ebtr2 ebtr1 ebtr0 30000dh config7h ? ebtrb ? ? ? ? ? ? legend: shaded cells are unimplemented. note 1: unimplemented in pic18fx525 devices. note: code protection bits may only be written to a ? 0 ? from a ? 1 ? state. it is not possible to write a ? 1 ? to a bit in the ? 0 ? state. code protection bits are only set to ? 1 ? by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp or an external programmer.
PIC18F6525/6621/8525/8621 ds39612b-page 272 ? 2005 microchip technology inc. figure 24-4: table write (wrtn) disallowed figure 24-5: external block t able read (ebtrn) disallowed 000000h 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh wrtb,ebtrb = 11 wrt0,ebtr0 = 01 wrt1,ebtr1 = 11 wrt2,ebtr2 = 11 wrt3,ebtr3 = 11 tblwt* tblptr = 000fffh pc = 003ffeh tblwt* pc = 008ffeh register values program memory configuration bit settings results: all table writes disabled to block n whenever wrtn = 0 . wrtb,ebtrb = 11 wrt0,ebtr0 = 10 wrt1,ebtr1 = 11 wrt2,ebtr2 = 11 wrt3,ebtr3 = 11 tblrd* tblptr = 000fffh pc = 004ffeh results: all table reads from external blocks to block n are disabled whenever ebtrn = 0 . tablat register returns a value of ? 0 ?. register values program memory configuration bit settings 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh 000000h
? 2005 microchip technology inc. ds39612b-page 273 PIC18F6525/6621/8525/8621 figure 24-6: external block table read (ebtrn) allowed 24.4.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits external writes to data eeprom. the cpu can continue to read data eeprom regardless of the protection bit settings. 24.4.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in user mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. wrtb,ebtrb = 11 wrt0,ebtr0 = 10 wrt1,ebtr1 = 11 wrt2,ebtr2 = 11 wrt3,ebtr3 = 11 tblrd* tblptr = 000fffh pc = 003ffeh register values program memory configuration bit settings results: table reads permitted within block n, even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr. 0007ffh 000800h 003fffh 004000h 007fffh 008000h 00bfffh 00c000h 00ffffh 000000h
PIC18F6525/6621/8525/8621 ds39612b-page 274 ? 2005 microchip technology inc. 24.5 id locations eight memory locations (200000h-200007h) are desig- nated as id locations where the user can store check- sum or other code identification numbers. these locations are accessible during normal execution through the tblrd and tblwt instructions, or during program/verify. the id locations can be read when the device is code-protected. 24.6 in-circuit serial programming? (icsp?) PIC18F6525/6621/8525/8621 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 24.7 in-circuit debugger when the debug bit in configuration register, config4l, is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 24-4 shows which features are consumed by the background debugger. table 24-4: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , gnd, rb7 and rb6. this will interface to the in-circuit debug- ger module available from microchip or one of the third party development tool companies. 24.8 low-voltage icsp programming the lvp bit in configuration register, config4l, enables low-voltage icsp programming. this mode allows the microcontroller to be programmed via icsp using a v dd source in the operating voltage range. this only means that v pp does not have to be brought to v ihh , but can instead be left at the normal operating voltage. in this mode, the rb5/kbi1/pgm pin is dedi- cated to the programming function and ceases to be a general purpose i/o pin. during programming, v dd is applied to the mclr /v pp pin. to enter programming mode, v dd must be applied to the rb5/kbi1/pgm pin provided the lvp bit is set. the lvp bit defaults to a ? 1 ? from the factory. if low-voltage programming mode is not used, the lvp bit can be programmed to a ? 0 ? and rb5/kbi1/pgm becomes a digital i/o pin. however, the lvp bit may only be programmed when programming is entered with v ihh on mclr /v pp . it should be noted that once the lvp bit is programmed to ? 0 ?, only the high-voltage programming mode is available and only high-voltage programming mode can be used to program the device. when using low-voltage icsp, the part must be supplied 4.5v to 5.5v if a bulk erase will be executed. this includes reprogramming of the code-protect bits from an on-state to off-state. for all other cases of low- voltage icsp, the part may be programmed at the normal operating voltage. this means unique user ids or user code can be reprogrammed or added. i/o pins rb6, rb7 stack 2 levels program memory 512 bytes data memory 10 bytes note 1: the high-voltage programming mode is always available, regardless of the state of the lvp bit, by applying v ihh to the mclr pin. 2: while in low-voltage icsp mode, the rb5 pin can no longer be used as a general purpose i/o pin and should be held low during normal operation. 3: when using low-voltage icsp program- ming (lvp) and the pull-ups on portb are enabled, bit 5 in the trisb register must be cleared to disable the pull-up on rb5 and ensure the proper operation of the device. 4: if the device master clear is disabled, verify that either of the following is done to ensure proper entry into icsp mode: a.) disable low-voltage programming (config4l<2> = 0 ); or b.) make certain that rb5/kbi1/pgm is held low during entry into icsp.
? 2005 microchip technology inc. ds39612b-page 275 PIC18F6525/6621/8525/8621 25.0 instruction set summary the pic18 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 25-2 lists byte-oriented , bit-oriented , literal and control operations. table 25-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file register is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register desig- nator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by ?k?) the desired fsr register to load the literal value into (specified by ?f?) no operand required (specified by ???) the control instructions may use some of the following operands: a program memory address (specified by ?n?) the mode of the call or return instructions (specified by ?s?) the mode of the table read and table write instructions (specified by ?m?) no operand required (specified by ???) all instructions are a single word, except for three double-word instructions. these three instructions were made double-word instructions so that all the required information is available in these 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle unless a conditional test is true, or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 25-1 shows the general formats that the instructions can have. all examples use the format ? nnh ? to represent a hexa- decimal number, where ? h ? signifies a hexadecimal digit. the instruction set summary, shown in table 25-2, lists the instructions recognized by the microchip mpasm tm assembler. section 25.1 ?instruction set? provides a description of each instruction.
PIC18F6525/6621/8525/8621 ds39612b-page 276 ? 2005 microchip technology inc. table 25-1: opcode field descriptions field description a ram access bit a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. d destination select bit d = 0 : store result in wreg d = 1 : store result in file register f dest destination either the wreg register or the specified register file location. f 8-bit register file address (0x00 to 0xff). fs 12-bit register file address (0x000 to 0xfff). this is the source address. fd 12-bit register file address (0x000 to 0x fff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for th e table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tb lptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions, or the direct address for call/ branch and return instructions. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) u unused or unchanged. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. tos top-of-stack. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. gie global interrupt enable bit. wdt watchdog timer. to time-out bit. pd power-down bit. c, dc, z, ov, n alu status bits: carry, digit carry, zero, overflow, negative. [ ] optional. ( ) contents. assigned to. < > register bit field. in the set of. italics user defined term (font is courier).
? 2005 microchip technology inc. ds39612b-page 277 PIC18F6525/6621/8525/8621 figure 25-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s
PIC18F6525/6621/8525/8621 ds39612b-page 278 ? 2005 microchip technology inc. table 25-2: pic18fxxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 bit-oriented file register operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as an input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 2005 microchip technology inc. ds39612b-page 279 PIC18F6525/6621/8525/8621 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 25-2: pic18fxxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as an input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
PIC18F6525/6621/8525/8621 ds39612b-page 280 ? 2005 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsrx 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 25-2: pic18fxxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as an input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, ?d? = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 2005 microchip technology inc. ds39612b-page 281 PIC18F6525/6621/8525/8621 25.1 instruction set addlw add literal to w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w to f syntax: [ label ] addwf f [,d [,a] f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr is used. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, 0, 0 before instruction w = 0x17 reg = 0xc2 after instruction w=0xd9 reg = 0xc2
PIC18F6525/6621/8525/8621 ds39612b-page 282 ? 2005 microchip technology inc. addwfc add w and carry bit to f syntax: [ label ] addwfc f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n, ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 0x02 w = 0x4d after instruction carry bit = 0 reg = 0x02 w = 0x50 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 0x5f before instruction w=0xa3 after instruction w = 0x03
? 2005 microchip technology inc. ds39612b-page 283 PIC18F6525/6621/8525/8621 andwf and w with f syntax: [ label ] andwf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?d? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, 0, 0 before instruction w = 0x17 reg = 0xc2 after instruction w = 0x02 reg = 0xc2 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here + 12) if carry = 0; pc = address (here + 2)
PIC18F6525/6621/8525/8621 ds39612b-page 284 ? 2005 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7, 0 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2)
? 2005 microchip technology inc. ds39612b-page 285 PIC18F6525/6621/8525/8621 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2)
PIC18F6525/6621/8525/8621 ds39612b-page 286 ? 2005 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2)
? 2005 microchip technology inc. ds39612b-page 287 PIC18F6525/6621/8525/8621 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7, 1 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a
PIC18F6525/6621/8525/8621 ds39612b-page 288 ? 2005 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f,b[,a] operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2005 microchip technology inc. ds39612b-page 289 PIC18F6525/6621/8525/8621 btg bit toggle f syntax: [ label ] btg f,b[,a] operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4, 0 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2)
PIC18F6525/6621/8525/8621 ds39612b-page 290 ? 2005 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos; k pc<20:1> if s = 1 (w) ws; (status) statuss; (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss= status
? 2005 microchip technology inc. ds39612b-page 291 PIC18F6525/6621/8525/8621 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f; 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg,1 before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt; 000h wdt postscaler; 1 to ; 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1
PIC18F6525/6621/8525/8621 ds39612b-page 292 ? 2005 microchip technology inc. comf complement f syntax: [ label ] comf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, 0, 0 before instruction reg = 0x13 after instruction reg = 0x13 w=0xec (f ) cpfseq compare f with w, skip if f = w syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (w); skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal)
? 2005 microchip technology inc. ds39612b-page 293 PIC18F6525/6621/8525/8621 cpfsgt compare f with w, skip if f > w syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w); skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w); skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless)
PIC18F6525/6621/8525/8621 ds39612b-page 294 ? 2005 microchip technology inc. daw decimal adjust w register syntax: [ label ] daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ] then (w<3:0>) + 6 w<3:0>; else ( w<3:0>) w<3:0> if [w<7:4> > 9] or [c = 1 ] then ( w<7:4>) + 6 w<7:4>; else (w<7:4>) w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=0xa5 c=0 dc = 0 after instruction w = 0x05 c=1 dc = 0 example 2: before instruction w=0xce c=0 dc = 0 after instruction w = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, 1, 0 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1
? 2005 microchip technology inc. ds39612b-page 295 PIC18F6525/6621/8525/8621 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest; skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest; skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero)
PIC18F6525/6621/8525/8621 ds39612b-page 296 ? 2005 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, 1, 0 before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1
? 2005 microchip technology inc. ds39612b-page 297 PIC18F6525/6621/8525/8621 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest; skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest; skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
PIC18F6525/6621/8525/8621 ds39612b-page 298 ? 2005 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf iorwf inclusive or w with f syntax: [ label ] iorwf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, 0, 1 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93
? 2005 microchip technology inc. ds39612b-page 299 PIC18F6525/6621/8525/8621 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, 0, 0 before instruction reg = 0x22 w=0xff after instruction reg = 0x22 w = 0x22
PIC18F6525/6621/8525/8621 ds39612b-page 300 ? 2005 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffff s ffff d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33 reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ?k? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 0x02 after instruction bsr register = 0x05
? 2005 microchip technology inc. ds39612b-page 301 PIC18F6525/6621/8525/8621 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg, 0 before instruction w = 0x4f reg = 0xff after instruction w = 0x4f reg = 0x4f
PIC18F6525/6621/8525/8621 ds39612b-page 302 ? 2005 microchip technology inc. mullw multiply literal with w syntax: [ label ] mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0xc4 before instruction w=0xe2 prodh = ? prodl = ? after instruction w=0xe2 prodh = 0xad prodl = 0x08 mulwf multiply w with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg, 1 before instruction w=0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction w=0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94
? 2005 microchip technology inc. ds39612b-page 303 PIC18F6525/6621/8525/8621 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using 2?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: negf reg, 1 before instruction reg = 0011 1010 [0x3a] after instruction reg = 1100 0110 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none.
PIC18F6525/6621/8525/8621 ds39612b-page 304 ? 2005 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down)= 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 00345ah pc = 000124h after instruction pc = 000126h tos = 000126h stack (1 level down)= 00345ah
? 2005 microchip technology inc. ds39612b-page 305 PIC18F6525/6621/8525/8621 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos; (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value
PIC18F6525/6621/8525/8621 ds39612b-page 306 ? 2005 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc; 1 gie/gieh or peie/giel if s = 1 (ws) w; (statuss) status; (bsrs) bsr; pclatu, pclath are unchanged status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: [ label ] retlw k operands: 0 k 255 operation: k w; (tos) pc; pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 0x07 after instruction w = value of kn
? 2005 microchip technology inc. ds39612b-page 307 PIC18F6525/6621/8525/8621 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc; if s = 1 (ws) w; (statuss) status; (bsrs) bsr; pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest; (f<7>) c; (c) dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 1100 1100 c=1 c register f
PIC18F6525/6621/8525/8621 ds39612b-page 308 ? 2005 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest; (f<7>) dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlncf reg, 1, 0 before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest; (f<0>) c; (c) dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rrcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 0111 0011 c=0 c register f
? 2005 microchip technology inc. ds39612b-page 309 PIC18F6525/6621/8525/8621 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest; (f<0>) dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2: rrncf reg, 0, 0 before instruction w=? reg = 1101 0111 after instruction w= 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f [,a] operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: setf reg,1 before instruction reg = 0x5a after instruction reg = 0xff
PIC18F6525/6621/8525/8621 ds39612b-page 310 ? 2005 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt postscaler; 1 to ; 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: [ label ] subfwb f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0
? 2005 microchip technology inc. ds39612b-page 311 PIC18F6525/6621/8525/8621 sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 0x02 before instruction w=1 c=? after instruction w=1 c = 1 ; result is positive z=0 n=0 example 2: sublw 0x02 before instruction w=2 c=? after instruction w=0 c = 1 ; result is zero z=1 n=0 example 3: sublw 0x02 before instruction w=3 c=? after instruction w = ff ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: [ label ] subwf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ;(2?s complement) w=2 c = 0 ; result is negative z=0 n=1
PIC18F6525/6621/8525/8621 ds39612b-page 312 ? 2005 microchip technology inc. subwfb subtract w from f with borrow syntax: [ label ] subwfb f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 0x19 (0001 1001) w = 0x0d (0000 1101) c=1 after instruction reg = 0x0c (0000 1011) w = 0x0d (0000 1101) c=1 z=0 n = 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 0x1b (0001 1011) w = 0x1a (0001 1010) c=0 after instruction reg = 0x1b (0001 1011) w = 0x00 c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 0x03 (0000 0011) w = 0x0e (0000 1101) c=1 after instruction reg = 0xf5 (1111 0100) ; [2?s comp] w = 0x0e (0000 1101) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: [ label ] swapf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>; (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg, 1, 0 before instruction reg = 0x53 after instruction reg = 0x35
? 2005 microchip technology inc. ds39612b-page 313 PIC18F6525/6621/8525/8621 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd* (prog mem (tblptr)) tablat; tblptr ? no change if tblrd*+ (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr if tblrd*- (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr if tblrd+* (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example 2: tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358
PIC18F6525/6621/8525/8621 ds39612b-page 314 ? 2005 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt* (tablat) holding register; tblptr ? no change if tblwt*+ (tablat) holding register; (tblptr) + 1 tblptr if tblwt*- (tablat) holding register; (tblptr) ? 1 tblptr if tblwt+* (tblptr) + 1 tblptr; (tablat) holding register status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 5.0 ?flash program memory? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment tblwt table write (continued) words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register ) example 1: tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 holding register (0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 holding register (0x00a356) = 0x55 example 2: tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a holding register (0x01389a) = 0xff holding register (0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b holding register (0x01389a) = 0xff holding register (0x01389b) = 0x34
? 2005 microchip technology inc. ds39612b-page 315 PIC18F6525/6621/8525/8621 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction, fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero) xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a
PIC18F6525/6621/8525/8621 ds39612b-page 316 ? 2005 microchip technology inc. xorwf exclusive or w with f syntax: [ label ] xorwf f [,d [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: xorwf reg, 1, 0 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
? 2005 microchip technology inc. ds39612b-page 317 PIC18F6525/6621/8525/8621 26.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? evaluation and programming tools - picdem msc -microid ? developer kits -can - powersmart ? developer kits -analog 26.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 26.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
PIC18F6525/6621/8525/8621 ds39612b-page 318 ? 2005 microchip technology inc. 26.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 26.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 26.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 26.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 26.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2005 microchip technology inc. ds39612b-page 319 PIC18F6525/6621/8525/8621 26.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 26.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 26.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. mplab pm3 connects to the host pc via an rs- 232 or usb cable. mplab pm3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an sd/mmc card for file storage and secure data appli- cations.
PIC18F6525/6621/8525/8621 ds39612b-page 320 ? 2005 microchip technology inc. 26.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 26.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 26.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 26.17 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 26.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 26.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide.
? 2005 microchip technology inc. ds39612b-page 321 PIC18F6525/6621/8525/8621 26.20 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 26.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 26.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 26.23 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit? flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 26.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 26.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product selector guide for the complete list of demonstration and evaluation kits.
PIC18F6525/6621/8525/8621 ds39612b-page 322 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 323 PIC18F6525/6621/8525/8621 27.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +5.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to v ss ............................................................................................................... 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
PIC18F6525/6621/8525/8621 ds39612b-page 324 ? 2005 microchip technology inc. figure 27-1: pic18f6x2x/8x2x voltage-frequency graph (industrial, extended) figure 27-2: pic18lf6x2x/8x2x voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v PIC18F6525/6621/8525/8621 4.2v (industrial) 25 mhz (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v 4 mhz 4.2v pic18lf6525/6621/8525/8621 for PIC18F6525/6621 and pic18f8525/8621 in microcontroller mode: f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz, if v ddappmin 4.2v; f max = 40 mhz, if v ddappmin > 4.2v. for pic18f8525/8621 in modes other than microcontroller mode: f max = (9.55 mhz/v) (v ddappmin ? 2.0v) + 4 mhz, if v ddappmin 4.2v; f max = 25 mhz, if v ddappmin > 4.2v. note: v ddappmin is the minimum voltage of the picmicro ? device in the application.
? 2005 microchip technology inc. ds39612b-page 325 PIC18F6525/6621/8525/8621 27.1 dc characteristics: supply voltage pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) pic18lf6x2x/8x2x (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x2x/8x2x (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions d001 v dd supply voltage pic18lf6x2x/8x2x 2.0 ? 5.5 v pic18f6x2x/8x2x 4.2 ? 5.5 v d001a av dd analog supply voltage -0.3 ? +0.3 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section 3.1 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 3.1 ?power-on reset (por)? for details d005 v bor brown-out reset voltage borv1:borv0 = 11 1.96 ? 2.18 v borv1:borv0 = 10 2.64 ? 2.92 v borv1:borv0 = 01 4.11 ? 4.55 v borv1:borv0 = 00 4.41 ? 4.87 v legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode or during a device reset without losing ram data.
PIC18F6525/6621/8525/8621 ds39612b-page 326 ? 2005 microchip technology inc. 27.2 dc characteristics: power-down and supply current pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) pic18lf6x2x/8x2x (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x2x/8x2x (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions power-down current (i pd ) (1) pic18lf6x2x/8x2x 0.2 1 a -40c v dd = 2.0v, (sleep mode) 0.2 1 a +25c 5.0 10 a +85c pic18lf6x2x/8x2x 0.4 1 a -40c v dd = 3.0v, (sleep mode) 0.4 1 a +25c 3.0 18 a +85c all devices 0.7 2 a -40c v dd = 5.0v, (sleep mode) 0.7 2 a +25c 15 32 a +85c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: the band gap reference is a shared re source used by both bor and lvd modules. enabling both modules will consume less than the specifie d sum current of the modules.
? 2005 microchip technology inc. ds39612b-page 327 PIC18F6525/6621/8525/8621 supply current (i dd ) (2,3) d010 pic18lf6x2x/8x2x 300 500 a -40c f osc = 1 mh z , ec oscillator 300 500 a+25c v dd = 2.0v 850 1000 a+85c pic18lf6x2x/8x2x 500 900 a -40c 500 900 a+25c v dd = 3.0v 11.5ma +85c all devices 1 2 ma -40c 12ma +25c v dd = 5.0v 1.3 3 ma +85c pic18lf6x2x/8x2x 1 2 ma -40c f osc = 4 mhz, ec oscillator 12ma +25c v dd = 2.0v 1.5 2.5 ma +85c pic18lf6x2x/8x2x 1.5 2 ma -40c 1.5 2 ma +25c v dd = 3.0v 22.5ma +85c all devices 3 5 ma -40c 35ma +25c v dd = 5.0v 46ma +85c 27.2 dc characteristics: power-down and supply current pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) (continued) pic18lf6x2x/8x2x (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x2x/8x2x (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: the band gap reference is a shared re source used by both bor and lvd modules. enabling both modules will consume less than the specifie d sum current of the modules.
PIC18F6525/6621/8525/8621 ds39612b-page 328 ? 2005 microchip technology inc. supply current (i dd ) (2,3) pic18f6x2x/8x2x 13 27 ma -40c f osc = 25 mh z , ec oscillator 15 27 ma +25c v dd = 4.2v 19 29 ma +85c pic18f6x2x/8x2x 17 31 ma -40c 21 31 ma +25c v dd = 5.0v 23 34 ma +85c pic18f6x2x/8x2x 20 34 ma -40c f osc = 40 mh z , ec oscillator 24 34 ma +25c v dd = 4.2v 29 44 ma +85c pic18f6x2x/8x2x 28 46 ma -40c 33 46 ma +25c v dd = 5.0v 40 51 ma +85c d014 pic18lf6x2x/8x2x 27 45 a -10c f osc = 32 khz, timer1 as clock 30 50 a+25c v dd = 2.0v 32 54 a+70c pic18lf6x2x/8x2x 33 55 a -10c 36 60 a+25c v dd = 3.0v 39 65 a+70c all devices 75 125 a -10c 90 150 a+25c v dd = 5.0v 113 188 a+70c 27.2 dc characteristics: power-down and supply current pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) (continued) pic18lf6x2x/8x2x (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x2x/8x2x (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: the band gap reference is a shared re source used by both bor and lvd modules. enabling both modules will consume less than the specifie d sum current of the modules.
? 2005 microchip technology inc. ds39612b-page 329 PIC18F6525/6621/8525/8621 module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer <1 2.0 a-40 c v dd = 2.0v <1 2 a+25 c 520 a+85 c 310 a-40 c v dd = 3.0v 320 a+25 c 10 35 a+85 c 12 25 a-40 c v dd = 5.0v 15 35 a+25 c 20 50 a+85 c d022a ( ? i bor ) brown-out reset (4) 55 115 a-40 c to +85 cv dd = 3.0v 105 175 a-40 c to +85 cv dd = 5.0v d022b ( ? i lvd ) low-voltage detect (4) 45 125 a-40 c to +85 cv dd = 2.0v 45 150 a-40 c to +85 cv dd = 3.0v 45 225 a-40 c to +85 cv dd = 5.0v d025 ( ? i oscb ) timer1 oscillator 20 27 a-10 c 20 30 a+25 cv dd = 2.0v 32 khz on timer1 25 35 a+70 c 22 60 a-10 c 22 65 a+25 cv dd = 3.0v 32 khz on timer1 25 75 a+70 c 30 75 a-10 c 30 85 a+25 cv dd = 5.0v 32 khz on timer1 35 100 a+70 c d026 ( ? i ad ) a/d converter <1 2 a+25 cv dd = 2.0v <1 2 a+25 cv dd = 3.0v a/d on, not converting <1 2 a+25 cv dd = 5.0v 27.2 dc characteristics: power-down and supply current pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) (continued) pic18lf6x2x/8x2x (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6x2x/8x2x (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: the band gap reference is a shared re source used by both bor and lvd modules. enabling both modules will consume less than the specifie d sum current of the modules.
PIC18F6525/6621/8525/8621 ds39612b-page 330 ? 2005 microchip technology inc. 27.3 dc characteristics: pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2 v dd 0.3 v dd v v d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hs+pll modes d033a osc1 v ss 0.2 v dd v rc, ec modes d033b osc1 v ss 0.3 v xt, lp modes d034 t1osi v ss 0.3 v v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8 v dd 0.7 v dd v dd v dd v v d042 mclr , osc1 (ec mode) 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hs+pll modes d043a osc1 0.8 v dd v dd vec mode d043b osc1 0.9 v dd v dd v rc mode (1) d043c osc1 1.6 v dd vxt, lp modes d044 t13cki 1.6 v dd v i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at high-impedance d061 mclr ? 5 av ss v pin v dd d063 osc1 ? 5 av ss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
? 2005 microchip technology inc. ds39612b-page 331 PIC18F6525/6621/8525/8621 v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc mode) ?0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd ? 0.7 ? v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc mode) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd ? 0.7 ? v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150 v od open-drain high voltage ? 8.5 v ra4 pin capacitive loading specs on output pins d100 (4) c osc2 osc2 pin ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c? mode 27.3 dc characteristics: pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min max units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
PIC18F6525/6621/8525/8621 ds39612b-page 332 ? 2005 microchip technology inc. table 27-1: comparator specifications table 27-2: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage 0 ? v dd ? 1.5 v d302 cmrr common mode rejection ratio 55 ? ? db 300 300a t resp response time (1) ? 150 400 600 ns ns pic18f6x2x/8x2x pic18lf6x2x/8x2x 301 t mc 2 ov comparator mode change to output valid ?? 10 s note 1: response time measured with one comparator input at (v dd ? 1.5)/2 while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +125c (unless otherwise stated) spec no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 v raa absolute accuracy ? ? 1/2 lsb d312 v rur unit resistor value (r) ? 2k ? ? 310 t set settling time (1) ? ? 10 s note 1: settling time measured while vrr = 1 and vr<3:0> transitions from 0000 to 1111 .
? 2005 microchip technology inc. ds39612b-page 333 PIC18F6525/6621/8525/8621 figure 27-3: low-voltage detect characteristics table 27-3: low-voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) low-voltage detect characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ? max units conditions d420 v lvd lvd voltage on v dd transition high-to-low lvv = 0000 ??? v lvv = 0001 1.96 2.06 2.16 v lvv = 0010 2.16 2.27 2.38 v lvv = 0011 2.35 2.47 2.59 v lvv = 0100 2.46 2.58 2.71 v lvv = 0101 2.64 2.78 2.92 v lvv = 0110 2.75 2.89 3.03 v lvv = 0111 2.95 3.10 3.26 v lvv = 1000 3.24 3.41 3.58 v lvv = 1001 3.43 3.61 3.79 v lvv = 1010 3.53 3.72 3.91 v lvv = 1011 3.72 3.92 4.12 v lvv = 1100 3.92 4.13 4.33 v lvv = 1101 4.11 4.33 4.55 v lvv = 1110 4.41 4.64 4.87 v d423 v bg band gap reference voltage value ? 1.22 ? v ? production tested at t amb = 25c. specifications over temp. limits ensured by characterization.
PIC18F6525/6621/8525/8621 ds39612b-page 334 ? 2005 microchip technology inc. table 27-4: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions internal program memory programming specifications d110 v pp voltage on mclr /v pp pin 9.00 ? 13.25 v (note 2) d112 i pp current into mclr /v pp pin ? ? 300 a d113 i ddp supply current during programming ??1.0ma data eeprom memory d120 e d byte endurance 100k 10k 1m 100k ? ? e/w e/w -40 c to +85 c -40 c to +125 c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 4 ? ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (1) 1m 100k 10m 1m ? ? e/w e/w -40c to +85c -40 c to +125 c program flash memory d130 e p cell endurance 10k 1k 100k 10k ? ? e/w e/w -40 c to +85 c -40 c to +125 c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v ie v dd for block erase 4.5 ? 5.5 v using icsp? port d132a v iw v dd for externally timed erase or write 4.5 ? 5.5 v using icsp port d132b v pew v dd for self-timed write and row erase v min ?5.5vv min = minimum operating voltage d133 t ie icsp block erase cycle time ? 4 ? ms v dd > 4.5v d133a t iw icsp erase or write cycle time (externally timed) 1??msv dd > 4.5v d133a t iw self-timed write cycle time ? 2 ? ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: refer to section 7.8 ?using the data eeprom? for a more detailed discussion on data eeprom endurance. 2: required only if low-voltage programming is disabled.
? 2005 microchip technology inc. ds39612b-page 335 PIC18F6525/6621/8525/8621 27.4 ac (timing) characteristics 27.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
PIC18F6525/6621/8525/8621 ds39612b-page 336 ? 2005 microchip technology inc. 27.4.2 timing conditions the temperature and voltages specified in table 27-5 apply to all timing specifications, unless otherwise noted. figure 27-4 specifies the load conditions for the timing specifications. table 27-5: temperature and voltage specifications ? ac figure 27-4: load conditions for devi ce timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 27.1 and section 27.3 . lf parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2
? 2005 microchip technology inc. ds39612b-page 337 PIC18F6525/6621/8525/8621 27.4.3 timing diagrams and specifications figure 27-5: external clock timing (all modes except pll) table 27-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 25 mhz ec, ecio (2) (-40oc to +85oc) dc 40 mhz ec, ecio dc 25 mhz ec, ecio (+85oc to +125oc) oscillator frequency (1) dc 4 mhz rc oscillator 0.1 4 mhz xt oscillator 4 25 mhz hs oscillator 4 10 mhz hs + pll oscillator 4 6.25 mhz hs + pll oscillator (2) 5 33 khz lp oscillator mode 1t osc external clki period (1) 25 ? ns ec, ecio 40 ? ns ec, ecio (2) 40 ? ns ec, ecio (+85oc to +125oc) oscillator period (1) 250 ? ns rc oscillator 250 10,000 ns xt oscillator 40 100 160 250 250 250 ns ns ns hs oscillator hs + pll oscillator hs + pll oscillator (2) 30 200 s lp oscillator 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc 3 tosl, tos h external clock in (osc1) high or low time 30 ? ns xt oscillator 2.5 ? s lp oscillator 10 ? ns hs oscillator 4tosr, tos f external clock in (osc1) rise or fall time ? 20 ns xt oscillator ? 50 ns lp oscillator ? 7.5 ns hs oscillator note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 2: PIC18F6525/6621/8525/8621 devices using external memory interface.
PIC18F6525/6621/8525/8621 ds39612b-page 338 ? 2005 microchip technology inc. table 27-7: pll clock timing specifications (v dd = 4.2 to 5.5v) figure 27-6: clko and i/o timing table 27-8: clko and i/o timing requirements param. no. sym characteristic min typ? max units conditions f osc oscillator frequency range 4 ? 10 mhz hs mode f sys on-chip v co system frequency 16 ? 40 mhz hs mode t rc pll start-up time (lock time) ? ? 2 ms ? clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 5v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. param no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 to clko ? 75 200 ns (note 1) 11 tosh2ckh osc1 to clko ? 75 200 ns (note 1) 12 tckr clko rise time ? 35 100 ns (note 1) 13 tckf clko fall time ? 35 100 ns (note 1) 14 tckl2iov clko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15 tiov2ckh port in valid before clko 0.25 t cy + 25 ? ? ns (note 1) 16 tckh2ioi port in hold after clko 0??ns (note 1) 17 tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) pic18f6x2x/8x2x 100 ? ? ns 18a pic18lf6x2x/8x2x 200 ? ? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 0 ? ? ns 20 tior port output rise time pic18f6x2x/8x2x ? 10 25 ns 20a pic18lf6x2x/8x2x ? ? 60 ns 21 tiof port output fall time pic18f6x2x/8x2x ? 10 25 ns 21a pic18lf6x2x/8x2x ? ? 60 ns 22? t inp int pin high or low time t cy ??ns 23? t rbp rb7:rb4 change int high or low time t cy ??ns 24? t rcp rc7:rc4 change int high or low time 20 ns ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc m ode, where clko output is 4 x t osc . note: refer to figure 27-4 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
? 2005 microchip technology inc. ds39612b-page 339 PIC18F6525/6621/8525/8621 figure 27-7: program memo ry read timing diagram table 27-9: program memory read timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5??ns 155 tall2oel ale to oe 10 0.125 t cy ?ns 160 tadz2oel ad high-z to oe (bus release to oe )0??ns 161 toeh2add oe to ad driven 0.125 t cy ? 5 ? ? ns 162 tadv2oeh ls data valid before oe (data setup time) 20 ? ? ns 163 toeh2adl oe to data in invalid (data hold time) 0 ? ? ns 164 talh2all ale pulse width ? 0.25 t cy ?ns 165 toel2oeh oe pulse width 0.5 t cy ? 5 0.5 t cy ?ns 166 talh2alh ale to ale (cycle time) 40 ns t cy ?ns 167 tacc address valid to data valid 0.75 t cy ? 25 ? ? ns 168 toe oe to data valid ? 0.5 t cy ? 25 ns 169 tall2oeh ale to oe 0.625 t cy ? 10 ? 0.625 t cy + 10 ns 171 talh2csl chip enable active to ale ??10ns 171a tubl2oeh ad valid to chip enable active 0.25 t cy ? 20 ? ? ns q1 q2 q3 q4 q1 q2 osc1 ale oe address data from external 164 166 160 165 161 151 162 163 ad<15:0> 167 168 155 address address 150 a<19:16> address 169 ba0 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
PIC18F6525/6621/8525/8621 ds39612b-page 340 ? 2005 microchip technology inc. figure 27-8: program memory write timing diagram table 27-10: program memory write timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5 ? ? ns 153 twrh2adl wrn to data out invalid (data hold time) 5 ? ? ns 154 twrl wrn pulse width 0.5 t cy ? 5 0.5 t cy ?ns 156 tadv2wrh data valid before wrn (data setup time) 0.5 t cy ? 10 ? ? ns 157 tbsv2wrl byte select valid before wrn (byte select setup time) 0.25 t cy ??ns 157a twrh2bsi wrn to byte select invalid (byte select hold time) 0.125 t cy ? 5 ? ? ns 166 talh2alh ale to ale (cycle time) ? t cy ?ns 171 talh2csl chip enable active to ale ??10ns 171a tubl2oeh ad valid to chip enable active 0.25 t cy ? 20 ? ? ns q1 q2 q3 q4 q1 q2 osc1 ale address data 156 150 151 153 ad<15:0> address wrh or wrl ub or lb 157 154 157a address a<19:16> address ba0 166 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
? 2005 microchip technology inc. ds39612b-page 341 PIC18F6525/6621/8525/8621 figure 27-9: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 27-10: brown-out reset timing table 27-11: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 71833ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 28 72 132 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 35 t bor brown-out reset pulse width 200 ? ? sv dd b vdd (see d005) 36 t irvst time for internal reference voltage to become stable ?2050 s 37 t lvd low-voltage detect pulse width 200 ? ? sv dd v lvd v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 27-4 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable
PIC18F6525/6621/8525/8621 ds39612b-page 342 ? 2005 microchip technology inc. figure 27-11: timer0 and timer1 external clock timings table 27-12: timer0 and timer1 external clock requirements note: refer to figure 27-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 param. no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or t cy + 40 n ? ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler pic18f6x2x/8x2x 10 ? ns pic18lf6x2x/8x2x 25 ? ns asynchronous pic18f6x2x/8x2x 30 ? ns pic18lf6x2x/8x2x 50 ? ns 46 tt1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler pic18f6x2x/8x2x 10 ? ns pic18lf6x2x/8x2x 25 ? ns asynchronous pic18f6x2x/8x2x 30 ? ns pic18lf6x2x/8x2x tbd tbd ns 47 tt1p t13cki input period synchronous greater of: 20 ns or t cy + 40 n ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 t13cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t13cki clock edge to timer increment 2 t osc 7 t osc ? legend: tbd = to be determined
? 2005 microchip technology inc. ds39612b-page 343 PIC18F6525/6621/8525/8621 figure 27-12: capture/compare/pwm timings (all eccp/ccp modules) table 27-13: capture/compare/pwm requirements (all eccp/ccp modules) note: refer to figure 27-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param. no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18f6x2x/8x2x 10 ? ns pic18lf6x2x/8x2x 20 ? ns 51 tcch ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18f6x2x/8x2x 10 ? ns pic18lf6x2x/8x2x 20 ? ns 52 tccp ccpx input period 3 t cy + 40 n ?nsn = prescale value (1,4 or 16) 53 tccr ccpx output rise time pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x ? 45 ns 54 tccf ccpx output fall time pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x ? 45 ns
PIC18F6525/6621/8525/8621 ds39612b-page 344 ? 2005 microchip technology inc. figure 27-13: parallel slave port timing (pic18f8525/8621) table 27-14: parallel slave port requirements (pic18f8525/8621) note: refer to figure 27-4 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param. no. symbol characteristic min max units conditions 62 tdtv2wrh data in valid before wr or cs (setup time) 20 25 ? ? ns ns extended temp. range 63 twrh2dti wr or cs to data?in invalid (hold time) pic18f6x2x/8x2x 20 ? ns pic18lf6x2x/8x2x 35 ? ns 64 trdl2dtv rd and cs to data?out valid ? ? 80 90 ns ns extended temp. range 65 trdh2dti rd or cs to data?out invalid 10 30 ns 66 tibfinh inhibit of the ibf flag bit being cleared from wr or cs ?3 t cy
? 2005 microchip technology inc. ds39612b-page 345 PIC18F6525/6621/8525/8621 figure 27-14: example spi? master mode timing (cke = 0 ) table 27-15: example spi? mode requirements (master mode, cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 27-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18f6x2x/8x2x ? 50 ns pic18lf6x2x/8x2x ? 100 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used.
PIC18F6525/6621/8525/8621 ds39612b-page 346 ? 2005 microchip technology inc. figure 27-15: example spi? master mode timing (cke = 1 ) table 27-16: example spi? mode requirements (master mode, cke = 1 ) param. no. symbol characteristic min max units conditions 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18f6x2x/8x2x ? 50 ns pic18lf6x2x/8x2x 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 27-4 for load conditions.
? 2005 microchip technology inc. ds39612b-page 347 PIC18F6525/6621/8525/8621 figure 27-16: example spi? slave mode timing (cke = 0 ) table 27-17: example spi? mode requirements (slave mode timing, cke = 0 ) param. no. symbol characteristic min max units conditions 70 tssl2sch, ts s l 2 s c l ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18f6x2x/8x2x ? 25 ns pic18f6x2x/8x2x 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output high-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18f6x2x/8x2x ? 25 ns pic18f6x2x/8x2x 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18f6x2x/8x2x ? 50 ns pic18f6x2x/8x2x 100 ns 83 tsch2ssh, ts c l 2 s s h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 27-4 for load conditions.
PIC18F6525/6621/8525/8621 ds39612b-page 348 ? 2005 microchip technology inc. figure 27-17: example spi? slave mode timing (cke = 1 ) table 27-18: example spi? slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ?ns 71 tsch sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output high-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18f6x2x/8x2x ? 25 ns pic18lf6x2x/8x2x ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18f6x2x/8x2x ? 50 ns pic18lf6x2x/8x2x ? 100 ns 82 tssl2dov sdo data output valid after ss edge pic18f6x2x/8x2x ? 50 ns pic18lf6x2x/8x2x ? 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 27-4 for load conditions.
? 2005 microchip technology inc. ds39612b-page 349 PIC18F6525/6621/8525/8621 figure 27-18: i 2 c? bus start/stop bits timing table 27-19: i 2 c? bus start/stop bits requirements (slave mode) figure 27-19: i 2 c? bus data timing note: refer to figure 27-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 27-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
PIC18F6525/6621/8525/8621 ds39612b-page 350 ? 2005 microchip technology inc. table 27-20: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18f6x2x/8x2x must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18f6x2x/8x2x must operate at a minimum of 10 mhz mssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18f6x2x/8x2x must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18f6x2x/8x2x must operate at a minimum of 10 mhz mssp module 1.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be used in a standard mode i 2 c bus system but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released.
? 2005 microchip technology inc. ds39612b-page 351 PIC18F6525/6621/8525/8621 figure 27-20: master ssp i 2 c? bus start/stop bits timing waveforms table 27-21: master ssp i 2 c? bus start/stop bits requirements figure 27-21: master ssp i 2 c? bus data timing note: refer to figure 27-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ns 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition hold time 100 khz mode 2(t osc )(brg + 1) ? ns 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 27-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
PIC18F6525/6621/8525/8621 ds39612b-page 352 ? 2005 microchip technology inc. table 27-22: master ssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102.+ parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the scl line is released.
? 2005 microchip technology inc. ds39612b-page 353 PIC18F6525/6621/8525/8621 figure 27-22: eusart synchronous transmissi on (master/slave) timing table 27-23: eusart synchronous transmission requirements figure 27-23: eusart synchronous receive (master/slave) timing table 27-24: eusart synchronous receive requirements 121 121 120 122 rc6/tx1/ck1 rc7/rx1/dt1 pin pin note: refer to figure 27-4 for load conditions. param. no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (master and slave) clock high to data out valid pic18f6x2x/8x2x ? 40 ns pic18lf6x2x/8x2x ? 100 ns 121 tckrf clock out rise time and fall time (master mode) pic18f6x2x/8x2x ? 20 ns pic18lf6x2x/8x2x ? 50 ns 122 tdtrf data out rise time and fall time pic18f6x2x/8x2x ? 20 ns pic18lf6x2x/8x2x ? 50 ns 125 126 rc6/tx1/ck1 rc7/rx1/dt1 pin pin note: refer to figure 27-4 for load conditions. param. no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (master and slave) data hold before ckx (dtx hold time) 10 ? ns 126 tckl2dtl data hold after ckx (dtx hold time) 15 ? ns
PIC18F6525/6621/8525/8621 ds39612b-page 354 ? 2005 microchip technology inc. table 27-25: a/d converter characteristics:pic18f6x2x/8x2x (industrial, extended) pic18lf6x2x/8x2x (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? ? ? 10 tbd bit bit v ref = v dd 3.0v v ref = v dd < 3.0v a03 e il integral linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a04 e dl differential linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a05 e fs full scale error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a06 e off offset error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a10 ? monotonicity guaranteed (3) ?v ss v ain v ref a20 v ref reference voltage (v refh ? v refl ) 0v ? ? v a20a 3v ? ? v for 10-bit resolution a21 v refh reference voltage high av ss ?av dd + 0.3v v a22 v refl reference voltage low av ss ? 0.3v ? av dd v a25 v ain analog input voltage av ss ? 0.3v ? v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ??10.0k ? a40 i ad a/d conversion current (v dd ) pic18f6x2x/8x2x ? 180 ? a average current consumption when a/d is on (note 1) pic18lf6x2x/8x2x ? 90 ? a a50 i ref v ref input current (note 2) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. legend: tbd = to be determined note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from ra2/an2/v ref - and ra3/an3/v ref + pins or av dd and av ss pins, whichever is selected as reference input. 2: vss v ain v ref 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
? 2005 microchip technology inc. ds39612b-page 355 PIC18F6525/6621/8525/8621 figure 27-24: a/d conversion timing table 27-26: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns) which also disconnects the holding capacitor from the analog input. . . . . . . t cy param. no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18f6x2x/8x2x 1.6 20 (5) st osc based, v ref 3.0v pic18lf6x2x/8x2x 3.0 20 (5) st osc based, v ref full range pic18f6x2x/8x2x 2.0 6.0 s a/d rc mode pic18lf6x2x/8x2x 3.0 9.0 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 1) 11 12 t ad 132 t acq acquisition time (note 3) 15 10 ? ? s s -40 c te m p +125 c 0 c tem p +125 c 135 t swc switching time from convert sample ? (note 4) 136 t amp amplifier settling time (note 2) 1? s this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 20.0 ?10-bit analog-to-digital converter (a/d) module? for minimum conditions when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance (r s ) on the input channels is 50 ? . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider.
PIC18F6525/6621/8525/8621 ds39612b-page 356 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 357 PIC18F6525/6621/8525/8621 28.0 dc and ac characteristics graphs and tables ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean ? 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 28-1: typical i dd vs. f osc over v dd (hs mode) figure 28-2: maximum i dd vs. f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 4 8 12 16 20 24 28 32 36 40 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c) 0 4 8 12 16 20 24 28 32 36 40 44 48 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c)
PIC18F6525/6621/8525/8621 ds39612b-page 358 ? 2005 microchip technology inc. figure 28-3: typical i dd vs. f osc over v dd (hs/pll mode) figure 28-4: maximum i dd vs. f osc over v dd (hs/pll mode) 0 4 8 12 16 20 24 28 32 36 40 45678910 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c) 0 5 10 15 20 25 30 35 40 45 45678910 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c)
? 2005 microchip technology inc. ds39612b-page 359 PIC18F6525/6621/8525/8621 figure 28-5: typical i dd vs. f osc over v dd (xt mode) figure 28-6: maximum i dd vs. f osc over v dd (xt mode) 0 1 2 3 4 5 00.511.522.533.54 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 1 2 3 4 5 6 7 00.511.522.533.54 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
PIC18F6525/6621/8525/8621 ds39612b-page 360 ? 2005 microchip technology inc. figure 28-7: typical i dd vs. f osc over v dd (lp mode) figure 28-8: maximum i dd vs. f osc over v dd (lp mode) lp mode, 25c 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 1 2 3 4 5 6 20 30 40 50 60 70 80 90 100 f osc (khz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2005 microchip technology inc. ds39612b-page 361 PIC18F6525/6621/8525/8621 figure 28-9: typical i dd vs. f osc over v dd (ec mode) figure 28-10: maximum i dd vs. f osc over v dd (ec mode) 0 4 8 12 16 20 24 28 32 36 40 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c) 0 4 8 12 16 20 24 28 32 36 40 44 48 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v 4.2v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +85c) minimum: mean ? 3 (-40c to +85c)
PIC18F6525/6621/8525/8621 ds39612b-page 362 ? 2005 microchip technology inc. figure 28-11: typical and maximum i t1osc vs. v dd (timer1 as system clock) figure 28-12: average f osc vs. v dd for various rs (rc mode, c = 20 pf, temp = 25c) 0 20 40 60 80 100 120 140 160 180 200 220 240 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd (ua) typ (25c) max (70c) typical: statistical mean @ 25c maximum: mean + 3 (-10c to +70c) minimum: mean ? 3 (-10c to +70c) 0 1,000 2,000 3,000 4,000 5,000 6,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (khz) 3.3k ? 5.1k ? 10k ? 100k ? operation above 4 mhz is not recomended. 3.3k ? 100 k ? 10 k ? 5.1 k ? 3.3 k ?
? 2005 microchip technology inc. ds39612b-page 363 PIC18F6525/6621/8525/8621 figure 28-13: average f osc vs. v dd for various rs (rc mode, c = 100 pf, temp = 25c) figure 28-14: average f osc vs. v dd for various rs (rc mode, c = 300 pf, temp = 25c) 100 k 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (khz) 3.3k ? 5.1k ? 10k ? 100k ? 3.3 k ? 5.1 k ? 10 k ? 100 k ? 0 100 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 3.3k ? 5.1k ? 10k ? 100k ? 3.3 k ? 5.1 k ? 10 k ? 100 k ?
PIC18F6525/6621/8525/8621 ds39612b-page 364 ? 2005 microchip technology inc. figure 28-15: i pd vs. v dd (sleep mode, all peripherals disabled) figure 28-16: typical and maximum ? i bor vs. v dd over temperature, v bor = 2.00-2.16v 0.01 0.1 1 10 100 1000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) max (-40c to +125c) typ (25c) max (85c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 50 100 150 200 250 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd (ua) max (+125c) max (+85c) typ (+25c) device held in reset device in sleep typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2005 microchip technology inc. ds39612b-page 365 PIC18F6525/6621/8525/8621 figure 28-17: i t 1 osc vs. v dd (sleep mode, timer1 and oscillator enabled) figure 28-18: i pd vs. v dd (sleep mode, wdt enabled) 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typ (25c) max (70c) typical: statistical mean @ 25c maximum: mean + 3 (-10c to +70c) minimum: mean ? 3 (-10c to +70c) 0.1 1 10 100 1000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) max (-40c to +125c) typ (25c) max (85c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
PIC18F6525/6621/8525/8621 ds39612b-page 366 ? 2005 microchip technology inc. figure 28-19: typical, minimum and maximum wdt period vs. v dd figure 28-20: ? i lvd vs. v dd over temperature, v lvd = 4.5-4.78v 0 5 10 15 20 25 30 35 40 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) wdt period (ms) max (125c) min (-40c) typ (25c) max (85c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 50 100 150 200 250 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) max (125c) typ (25c) max (125c) typ (25c) lvdif is set by hardware lvdif can be cleared by firmware lvdif state is unknown typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2005 microchip technology inc. ds39612b-page 367 PIC18F6525/6621/8525/8621 figure 28-21: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 c to +125 c) figure 28-22: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (-ma) v oh (v) typ (25c) max min max typ (+25c) min 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (-ma) v oh (v) typ (25c) max min typ (+25c) min max
PIC18F6525/6621/8525/8621 ds39612b-page 368 ? 2005 microchip technology inc. figure 28-23: typical and maximum v ol vs. i ol (v dd = 5v, -40 c to +125 c) figure 28-24: typical and maximum v ol vs. i ol (v dd = 3v, -40 c to +125 c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 5 10 15 20 25 i ol (-ma) v ol (v) max typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) typ (+25c) max 0.0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 i ol (-ma) v ol (v) max typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) typ (+25c) max
? 2005 microchip technology inc. ds39612b-page 369 PIC18F6525/6621/8525/8621 figure 28-25: minimum and maximum v in vs. v dd (st input, -40 c to +125 c) figure 28-26: minimum and maximum v in vs. v dd (ttl input, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max v ih min v il max v il min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v th (max) v th (min) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
PIC18F6525/6621/8525/8621 ds39612b-page 370 ? 2005 microchip technology inc. figure 28-27: minimum and maximum v in vs. v dd (i 2 c input, -40 c to +125 c) figure 28-28: a/d nonlinearity vs. v refh (v dd = v refh , -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max v ih min v il max v il min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) v il max 0 0.5 1 1.5 2 2.5 3 3.5 4 22.533.544.555.5 v dd and v refh (v) differential or integral nonlinearity (lsb) -40c 25c 85c 125c -40c +25c +85c +125c
? 2005 microchip technology inc. ds39612b-page 371 PIC18F6525/6621/8525/8621 figure 28-29: a/d nonlinearity vs. v refh (v dd = 5v, -40 c to +125 c) 0 0.5 1 1.5 2 2.5 3 22.533.544.555.5 v refh (v) differential or integral nonlinearilty (lsb) max (-40c to 125c) typ (25c) typ (+25c) max (-40c to +125c)
PIC18F6525/6621/8525/8621 ds39612b-page 372 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 373 PIC18F6525/6621/8525/8621 29.0 packaging information 29.1 package marking information 64-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f6621 -i/pt 0410017 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f8621 -e/pt 0410017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e
PIC18F6525/6621/8525/8621 ds39612b-page 374 ? 2005 microchip technology inc. 29.2 package details the following sections give the technical details of the packages. 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-085 *controlling parameter
? 2005 microchip technology inc. ds39612b-page 375 PIC18F6525/6621/8525/8621 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-092 *controlling parameter
PIC18F6525/6621/8525/8621 ds39612b-page 376 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 377 PIC18F6525/6621/8525/8621 appendix a: revision history revision a (july 2003) original data sheet for PIC18F6525/6621/8525/8621 family. revision b (august 2004) this revision includes updates to the electrical specifi- cations in section 27.0 , the dc and ac characteristics graphs and tables in section 28.0 have been added and includes minor corrections to the data sheet text. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences feature PIC18F6525 pic18f6621 pic18f8525 pic18f8621 on-chip program memory (kbytes) 48k 64k 48k 64k i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h, j a/d channels 12 12 16 16 external memory interface no no yes yes package types 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
PIC18F6525/6621/8525/8621 ds39612b-page 378 ? 2005 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for con- verting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic17c756 to a pic18f8720. not applicable appendix d: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442 .? the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716.
? 2005 microchip technology inc. ds39612b-page 379 PIC18F6525/6621/8525/8621 appendix e: migration from high-end to enhanced devices a detailed discussion of the migration pathway and dif- ferences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration .? this application note is available as literature number ds00726.
PIC18F6525/6621/8525/8621 ds39612b-page 380 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds39612b-page 381 PIC18F6525/6621/8525/8621 index a a/d .................................................................................... 233 acquisition requirements ......................................... 238 acquisition time........................................................ 238 adcon0 register..................................................... 233 adcon1 register..................................................... 233 adcon2 register..................................................... 233 adresh register............................................. 233, 236 adresl register ............................................. 233, 236 analog port pins ....................................................... 128 analog port pins, configuring................................... 240 associated register summary.................................. 241 automatic acquisition time....................................... 239 calculating minimum required acquisition time ............................................... 238 configuring the module............................................. 237 conversion clock (t ad ) ............................................ 239 conversion status (go/done bit) ........................... 236 conversion t ad cycles............................................. 240 conversions .............................................................. 240 converter characteristics ......................................... 354 converter interrupt, configuring ............................... 237 eccp2 special event trigger................................... 241 equations .................................................................. 238 minimum charging time........................................... 238 selecting and configuring acquisition time ............................................... 239 special event trigger (eccp) .................................. 160 t ad vs. device operating frequencies (table) ........................................... 239 absolute maximum ratings .............................................. 323 ac (timing) characteristics .............................................. 335 load conditions for device timing specifications........................................ 336 parameter symbology .............................................. 335 temperature and voltage specifications.................................................... 336 timing conditions ..................................................... 336 ackstat ......................................................................... 203 ackstat status flag ...................................................... 203 adcon0 register............................................................. 233 go/done bit............................................................ 236 adcon1 register............................................................. 233 adcon2 register............................................................. 233 addlw ............................................................................. 281 addwf ............................................................................. 281 addwfc .......................................................................... 282 adresh register..................................................... 233, 236 adresl register ..................................................... 233, 236 analog-to-digital converter. see a/d. andlw ............................................................................. 282 andwf ............................................................................. 283 assembler mpasm assembler................................................... 317 auto-wake-up on sync break character .......................... 225 b baud rate generator ........................................................ 199 bc ..................................................................................... 283 bcf ................................................................................... 284 bf ..................................................................................... 203 bf status flag .................................................................. 203 block diagrams 16-bit byte select mode ............................................. 75 16-bit byte write mode............................................... 73 16-bit word write mode ............................................. 74 a/d............................................................................ 236 analog input model................................................... 237 baud rate generator ............................................... 199 capture mode operation .......................................... 151 comparator analog input model............................... 247 comparator i/o operating modes ............................ 244 comparator output................................................... 246 comparator voltage reference................................ 250 comparator voltage reference output buffer example ..................................... 251 compare mode operation ........................................ 152 enhanced pwm........................................................ 161 eusart receive ..................................................... 223 eusart transmit .................................................... 221 low-voltage detect (lvd)........................................ 254 low-voltage detect with external input.................... 254 mclr /v pp /rg5 pin.................................................. 121 mssp (i 2 c master mode)......................................... 197 mssp (i 2 c mode)..................................................... 182 mssp (spi mode) .................................................... 173 on-chip reset circuit................................................. 29 PIC18F6525/6621 ........................................................ 9 pic18f8525/8621 ...................................................... 10 pll ............................................................................. 23 port/lat/tris operation ......................................... 103 portc (peripheral output override)....................... 109 portd and porte (parallel slave port)................ 128 portd in i/o port mode.......................................... 111 portd in system bus mode ................................... 112 porte in i/o mode.................................................. 115 porte in system bus mode ................................... 115 portg (peripheral output override) ...................... 120 portj in i/o mode .................................................. 125 pwm operation (simplified) ..................................... 154 ra3:ra0 and ra5 pins............................................ 104 ra4/t0cki pin ......................................................... 104 ra6 pin (enabled as i/o) ......................................... 104 rb2:rb0 pins........................................................... 107 rb3 pin .................................................................... 107 rb7:rb4 pins........................................................... 106 reads from flash program memory .......................... 65 rf1/an6/c2out and rf2/an7/c1out pins.......... 117 rf6:rf3 and rf0 pins ............................................ 118 rf7 pin..................................................................... 118 rh3:rh0 pins in i/o mode....................................... 122 rh3:rh0 pins in system bus mode ........................ 123 rh7:rh4 pins in i/o mode....................................... 122 rj4:rj0 pins in system bus mode.......................... 126 rj7:rj6 pins in system bus mode.......................... 126 single comparator.................................................... 245 table read operation ................................................ 61 table write operation ................................................ 62 table writes to flash program memory ..................... 67 timer0 in 16-bit mode .............................................. 132 timer0 in 8-bit mode ................................................ 132 timer1 ...................................................................... 136 timer1 (16-bit read/write mode)............................. 136 timer2 ...................................................................... 142
PIC18F6525/6621/8525/8621 ds39612b-page 382 ? 2005 microchip technology inc. timer3 ....................................................................... 144 timer3 (16-bit read/write mode) ............................. 144 timer4 ....................................................................... 148 watchdog timer........................................................ 268 bn ..................................................................................... 284 bnc................................................................................... 285 bnn................................................................................... 285 bnov ................................................................................ 286 bnz ................................................................................... 286 bor. see brown-out reset. bov................................................................................... 289 bra................................................................................... 287 break character (12-bit) transmit and receive ............... 226 brg. see baud rate generator. brown-out reset (bor) .............................................. 30, 259 bsf ................................................................................... 287 btfsc .............................................................................. 288 btfss............................................................................... 288 btg................................................................................... 289 bz...................................................................................... 290 c c compilers mplab c17 .............................................................. 318 mplab c18 .............................................................. 318 mplab c30 .............................................................. 318 call ................................................................................. 290 capture (ccp module)...................................................... 151 associated registers ................................................ 153 ccp pin configuration .............................................. 151 ccpr4h:ccpr4l registers.................................... 151 software interrupt ..................................................... 151 timer1/timer3 mode selection ................................. 151 capture (eccp module) ................................................... 160 capture/compare/pwm (ccp)......................................... 149 capture mode. see capture. ccp mode and timer resources ............................. 150 ccprxh register ..................................................... 150 ccprxl register...................................................... 150 compare mode. see compare. interconnect configurations ...................................... 150 module configuration ................................................ 150 pwm mode. see pwm. clocking scheme/instruction cycle..................................... 44 clrf................................................................................. 291 clrwdt........................................................................... 291 code examples 16 x 16 signed multiply routine ................................. 86 16 x 16 unsigned multiply routine ............................. 86 8 x 8 signed multiply routine ..................................... 85 8 x 8 unsigned multiply routine ................................. 85 changing between capture prescalers .................... 151 computed goto using an offset value .................... 46 data eeprom read .................................................. 81 data eeprom refresh routine ................................. 82 data eeprom write .................................................. 81 erasing a flash program memory row ...................... 66 fast register stack..................................................... 44 how to clear ram (bank 1) using indirect addressing ............................................. 56 implementing a real-time clock using a timer1 interrupt service ................................... 138 initializing porta..................................................... 103 initializing portb..................................................... 106 initializing portc..................................................... 109 initializing portd..................................................... 111 initializing porte..................................................... 114 initializing portf..................................................... 117 initializing portg .................................................... 120 initializing porth .................................................... 122 initializing portj ..................................................... 125 loading the sspbuf (sspsr) register.................. 176 reading a flash program memory word ................... 65 saving status, wreg and bsr registers in ram ..................................... 102 writing to flash program memory ........................ 68?69 code protection ........................................................ 259, 270 associated registers ................................................ 271 configuration register protection............................. 273 data eeprom.......................................................... 273 program memory ...................................................... 271 comf ............................................................................... 292 comparator....................................................................... 243 analog input connection considerations ................. 247 associated registers ................................................ 248 configuration ............................................................ 244 effects of a reset ..................................................... 247 interrupts .................................................................. 246 operation .................................................................. 245 operation during sleep ............................................ 247 outputs ..................................................................... 245 reference ................................................................. 245 external signal ................................................. 245 internal signal................................................... 245 response time......................................................... 245 comparator specifications................................................ 332 comparator voltage reference ........................................ 249 accuracy and error ................................................... 250 associated registers ................................................ 251 configuring ............................................................... 249 connection considerations....................................... 250 effects of a reset ..................................................... 250 operation during sleep ............................................ 250 compare (ccp module) ................................................... 152 associated registers ................................................ 153 ccp pin configuration.............................................. 152 ccpr1 register ....................................................... 152 software interrupt ..................................................... 152 special event trigger ............................................... 152 timer1/timer3 mode selection................................. 152 compare (eccp module)................................................. 160 special event trigger ............................... 137, 145, 160 configuration bits ............................................................. 259 context saving during interrupts...................................... 102 control registers eecon1 and eecon2 .............................................. 62 tablat (table latch) register.................................. 64 tblptr (table pointer) register............................... 64 conversion considerations............................................... 378 cpfseq ........................................................................... 292 cpfsgt ........................................................................... 293 cpfslt ............................................................................ 293 d data eeprom memory...................................................... 79 associated registers .................................................. 83 eeadr register ......................................................... 79 eeadrh register ...................................................... 79 eecon1 register....................................................... 79 eecon2 register....................................................... 79 operation during code-protect .................................. 82 protection against spurious write .............................. 82
? 2005 microchip technology inc. ds39612b-page 383 PIC18F6525/6621/8525/8621 reading....................................................................... 81 using........................................................................... 82 write verify ................................................................. 82 writing to.................................................................... 81 data memory ...................................................................... 47 general purpose registers......................................... 47 map for pic18f6x2x/8x2x devices .......................... 48 special function registers ......................................... 47 daw.................................................................................. 294 dc and ac characteristics graphs and tables ................................................... 357 dc characteristics ............................................................ 330 power-down and supply current ............................. 326 supply voltage.......................................................... 325 dcfsnz ........................................................................... 295 decf ................................................................................ 294 decfsz............................................................................ 295 demonstration boards picdem 1 ................................................................. 320 picdem 17 ............................................................... 321 picdem 18r ............................................................ 321 picdem 2 plus ......................................................... 320 picdem 3 ................................................................. 320 picdem 4 ................................................................. 320 picdem lin ............................................................. 321 picdem usb............................................................ 321 picdem.net internet/ethernet .................................. 320 development support ....................................................... 317 device differences............................................................ 377 direct addressing................................................................ 57 direct addressing........................................................ 55 e eccp capture and compare modes................................... 160 standard pwm mode................................................ 160 electrical characteristics................................................... 323 enhanced capture/compare/pwm (eccp) ..................... 157 and program memory modes ................................... 158 capture mode. see capture (eccp module). outputs and configuration ........................................ 158 pin configurations for eccp1 .................................. 158 pin configurations for eccp2 .................................. 159 pin configurations for eccp3 .................................. 159 pwm mode. see pwm (eccp module). timer resources....................................................... 160 use with ccp4 and ccp5 ........................................ 158 enhanced pwm mode. see pwm (eccp module). enhanced universal synchronous asynchronous receiver transmitter (eusart)............................... 213 errata .................................................................................... 5 eusart asynchronous mode ................................................. 221 12-bit break transmit and receive .................. 226 associated registers, receive ......................... 224 associated registers, transmit ........................ 222 auto-wake-up on sync break .......................... 225 receiver............................................................ 223 setting up 9-bit mode with address detect ......................................... 223 transmitter........................................................ 221 baud rate generator (brg) .................................... 217 associated registers........................................ 217 auto-baud rate detect..................................... 220 baud rate error, calculating............................ 217 baud rates, asynchronous modes .................. 218 high baud rate select (brgh bit) .................. 217 sampling .......................................................... 217 synchronous master mode....................................... 227 associated registers, receive......................... 230 associated registers, transmit........................ 228 reception ......................................................... 229 transmission .................................................... 227 synchronous slave mode......................................... 231 associated registers, receive......................... 232 associated registers, transmit........................ 231 reception ......................................................... 232 transmission .................................................... 231 evaluation and programming tools.................................. 321 extended microcontroller mode .......................................... 71 external memory interface.................................................. 71 16-bit byte select mode ............................................. 75 16-bit byte write mode............................................... 73 16-bit mode ................................................................ 73 16-bit mode timing .................................................... 76 16-bit word write mode ............................................. 74 pic18f8x2x external bus - i/o port functions............................................... 72 program memory modes and external memory interface................................................ 71 f flash program memory ...................................................... 61 associated registers.................................................. 69 control registers........................................................ 62 erase sequence ......................................................... 66 erasing ....................................................................... 66 operation during code-protect .................................. 69 reading ...................................................................... 65 table pointer boundaries based on operation ........................ 64 table pointer boundaries ........................................... 64 table reads and table writes ................................... 61 write sequence .......................................................... 67 writing to ................................................................... 67 protection against spurious writes .................... 69 unexpected termination .................................... 69 write verify ......................................................... 69 g general call address support .......................................... 196 goto ............................................................................... 296 h hardware multiplier............................................................. 85 introduction................................................................. 85 operation.................................................................... 85 performance comparison........................................... 85
PIC18F6525/6621/8525/8621 ds39612b-page 384 ? 2005 microchip technology inc. i i/o ports ............................................................................ 103 i 2 c mode associated registers ................................................ 212 general call address support .................................. 196 master mode operation .......................................................... 198 master mode transmit sequence ............................. 198 read/write bit information (r/w bit) ................ 186, 187 serial clock (rc3/sck/scl).................................... 187 id locations .............................................................. 259, 274 incf.................................................................................. 296 incfsz ............................................................................. 297 in-circuit debugger ........................................................... 274 resources (table)...................................................... 274 in-circuit serial programming (icsp) ....................... 259, 274 indirect addressing ............................................................. 57 indf and fsr registers ............................................ 56 operation .................................................................... 56 indirect addressing operation............................................. 57 indirect file operand........................................................... 47 infsnz ............................................................................. 297 initialization conditions for all registers ....................... 32?36 instruction flow/pipelining .................................................. 45 instruction set addlw ..................................................................... 281 addwf ..................................................................... 281 addwfc .................................................................. 282 andlw ..................................................................... 282 andwf ..................................................................... 283 bc ............................................................................. 283 bcf ........................................................................... 284 bn ............................................................................. 284 bnc .......................................................................... 285 bnn .......................................................................... 285 bnov ........................................................................ 286 bnz ........................................................................... 286 bov .......................................................................... 289 bra........................................................................... 287 bsf ........................................................................... 287 btfsc ...................................................................... 288 btfss ...................................................................... 288 btg........................................................................... 289 bz ............................................................................. 290 call ......................................................................... 290 clrf......................................................................... 291 clrwdt................................................................... 291 comf ....................................................................... 292 cpfseq ................................................................... 292 cpfsgt ................................................................... 293 cpfslt .................................................................... 293 daw.......................................................................... 294 dcfsnz ................................................................... 295 decf ........................................................................ 294 decfsz.................................................................... 295 firmware instructions................................................ 275 general format......................................................... 277 goto ....................................................................... 296 incf.......................................................................... 296 incfsz ..................................................................... 297 infsnz ..................................................................... 297 iorlw ...................................................................... 298 iorwf ...................................................................... 298 lfsr ......................................................................... 299 movf ....................................................................... 299 movff ..................................................................... 300 movlb ..................................................................... 300 movlw .................................................................... 301 movwf .................................................................... 301 mullw..................................................................... 302 mulwf..................................................................... 302 negf........................................................................ 303 nop .......................................................................... 303 opcode field descriptions........................................ 276 pop .......................................................................... 304 push........................................................................ 304 rcall ...................................................................... 305 reset...................................................................... 305 retfie ..................................................................... 306 retlw ..................................................................... 306 return................................................................... 307 rlcf ........................................................................ 307 rlncf...................................................................... 308 rrcf........................................................................ 308 rrncf ................................... .................................. 309 setf ........................................................................ 309 sleep ...................................................................... 310 subfwb .................................................................. 310 sublw ..................................................................... 311 subwf..................................................................... 311 subwfb .................................................................. 312 swapf ..................................................................... 312 tblrd ...................................................................... 313 tblwt ..................................................................... 314 tstfsz .................................................................... 315 xorlw .................................................................... 315 xorwf .................................................................... 316 summary table ........................................................ 278 int interrupt (rb3/int3:rb0/int0). see interrupt sources. intcon registers.............................................................. 89 inter-integrated circuit. see i 2 c. interrupt logic (diagram) .................................................... 88 interrupt sources .............................................................. 259 a/d conversion complete ........................................ 237 capture complete (ccp).......................................... 151 compare complete (ccp)........................................ 152 int0 .......................................................................... 102 interrupt-on-change (rb7:rb4) ............................... 106 portb, interrupt-on-change ................................... 102 rb3/int3:rb0/int0/flt0 pins, external................. 102 tmr0 ........................................................................ 102 tmr0 overflow......................................................... 133 tmr1 overflow................................................. 135, 137 tmr2 to pr2 match ................................................. 142 tmr2 to pr2 match (pwm) ..................... 141, 154, 160 tmr3 overflow................................................. 143, 145 tmr4 to pr4 match ................................................. 148 tmr4 to pr4 match (pwm) ..................................... 147 interrupts............................................................................. 87 control registers ........................................................ 89 enable registers ........................................................ 95 flag registers............................................................. 92 priority registers ........................................................ 98 reset control registers............................................ 101 iorlw .............................................................................. 298 iorwf.............................................................................. 298 ipr registers...................................................................... 98
? 2005 microchip technology inc. ds39612b-page 385 PIC18F6525/6621/8525/8621 k key features easy migration .............................................................. 7 expanded memory........................................................ 7 external memory interface............................................ 7 other special features ................................................. 7 l lfsr ................................................................................. 299 low-voltage detect........................................................... 253 characteristics .......................................................... 333 converter characteristics ......................................... 333 effects of a reset...................................................... 257 operation .................................................................. 256 current consumption........................................ 257 during sleep ..................................................... 257 reference voltage set point ............................ 257 typical application .................................................... 253 low-voltage icsp programming ...................................... 274 lvd. see low-voltage detect. m master ssp (mssp) module overview ............................ 173 master synchronous serial port (mssp). see mssp. master synchronous serial port. see mssp memory mode memory access ................................................ 40 memory maps for pic18f6x2x/8x2x program memory modes ............................................ 41 memory organization data memory .............................................................. 47 program memory ........................................................ 39 modes ................................................................. 39 memory programming requirements ............................... 334 microcontroller mode .......................................................... 71 microprocessor mode ......................................................... 71 microprocessor with boot block mode ................................ 71 migration from high-end to enhanced devices .................................................... 379 migration from mid-range to enhanced devices .................................................... 378 movf................................................................................ 299 movff ............................................................................. 300 movlb ............................................................................. 300 movlw ............................................................................ 301 movwf ............................................................................ 301 mplab asm30 assembler, linker, librarian ................... 318 mplab icd 2 in-circuit debugger ................................... 319 mplab ice 2000 high-performance universal in-circuit emulator .................................... 319 mplab ice 4000 high-performance universal in-circuit emulator .................................... 319 mplab integrated development environment software............................................... 317 mplab pm3 device programmer .................................... 319 mplink object linker/mplib object librarian ................ 318 mssp ................................................................................ 173 ack pulse......................................................... 186, 187 clock stretching........................................................ 192 10-bit slave receive mode (sen = 1).............. 192 10-bit slave transmit mode ............................. 192 7-bit slave receive mode (sen = 1)................ 192 7-bit slave transmit mode ............................... 192 clock synchronization and the ckp bit (sen = 1)............................................. 193 control registers (general) ...................................... 173 enabling spi i/o ....................................................... 177 i 2 c mode .................................................................. 182 acknowledge sequence timing ....................... 206 baud rate generator ....................................... 199 bus collision during a repeated start condition.................................. 210 bus collision during a start condition ............. 208 bus collision during a stop condition.............. 211 clock arbitration ............................................... 200 effect of a reset ............................................... 207 i 2 c clock rate w/brg ..................................... 199 master mode..................................................... 197 reception ................................................. 203 repeated start condition timing ............. 202 start condition timing.............................. 201 transmission ............................................ 203 multi-master communication, bus collision and arbitration ........................... 207 multi-master mode............................................ 207 registers .......................................................... 182 sleep operation ............................................... 207 stop condition timing ...................................... 206 module operation ..................................................... 186 operation.................................................................. 176 slave mode............................................................... 186 addressing ....................................................... 186 reception ......................................................... 187 transmission .................................................... 187 spi master mode...................................................... 178 spi mode.................................................................. 173 spi slave mode........................................................ 179 sspbuf ................................................................... 178 sspsr ..................................................................... 178 tmr2 output for clock shift............................. 141, 142 tmr4 output for clock shift..................................... 148 typical connection ................................................... 177 mssp module spi master/slave connection................................... 177 mullw............................................................................. 302 mulwf............................................................................. 302 n negf................................................................................ 303 nop .................................................................................. 303 o oscillator configuration ................. ..................................... 21 ec............................................................................... 21 ecio........................................................................... 21 ecio+pll .................................................................. 21 ecio+spll ................................................................ 21 hs............................................................................... 21 hs+pll ...................................................................... 21 hs+spll.................................................................... 21 lp ............................................................................... 21 rc .............................................................................. 21 rcio........................................................................... 21 xt ............................................................................... 21 oscillator selection ........................................................... 259 oscillator, timer1.............................................. 135, 137, 145 oscillator, timer3.............................................................. 143 oscillator, wdt................................................................. 267
PIC18F6525/6621/8525/8621 ds39612b-page 386 ? 2005 microchip technology inc. p packaging ......................................................................... 373 details ....................................................................... 374 marking ..................................................................... 373 parallel slave port (psp) .......................................... 111, 128 associated registers ................................................ 130 re0/ad8/rd /p2d pin............................................... 128 re1/ad9/wr /p2c pin .............................................. 128 re2/ad10/cs /p2b pin ............................................. 128 select (pspmode bit) ..................................... 111, 128 phase locked loop (pll)................................................... 23 pickit 1 flash starter kit................................................... 321 picstart plus development programmer ..................... 320 pie registers ...................................................................... 95 pin functions av dd ........................................................................... 20 av ss ........................................................................... 20 mclr /v pp /rg5 .......................................................... 11 osc1/clki ................................................................. 11 osc2/clko/ra6 ....................................................... 11 ra0/an0 ..................................................................... 12 ra1/an1 ..................................................................... 12 ra2/an2/v ref -........................................................... 12 ra3/an3/v ref +.......................................................... 12 ra4/t0cki .................................................................. 12 ra5/an4/lvdin ......................................................... 12 ra6 ............................................................................. 12 rb0/int0/flt0 ........................................................... 13 rb1/int1 .................................................................... 13 rb2/int2 .................................................................... 13 rb3/int3/eccp2/p2a ............................................... 13 rb4/kbi0 .................................................................... 13 rb5/kbi1/pgm ........................................................... 13 rb6/kbi2/pgc ........................................................... 13 rb7/kbi3/pgd ........................................................... 13 rc0/t1oso/t13cki .................................................. 14 rc1/t1osi/eccp2/p2a............................................. 14 rc2/eccp1/p1a ........................................................ 14 rc3/sck/scl ............................................................ 14 rc4/sdi/sda ............................................................. 14 rc5/sdo .................................................................... 14 rc6/tx1/ck1 ............................................................. 14 rc7/rx1/dt1 ............................................................. 14 rd0/ad0/psp0........................................................... 15 rd1/ad1/psp1........................................................... 15 rd2/ad2/psp2........................................................... 15 rd3/ad3/psp3........................................................... 15 rd4/ad4/psp4........................................................... 15 rd5/ad5/psp5........................................................... 15 rd6/ad6/psp6........................................................... 15 rd7/ad7/psp7........................................................... 15 re0/ad8/rd /p2d ....................................................... 16 re1/ad9/wr /p2c ...................................................... 16 re2/ad10/cs /p2b ..................................................... 16 re3/ad11/p3c ........................................................... 16 re4/ad12/p3b ........................................................... 16 re5/ad13/p1c ........................................................... 16 re6/ad14/p1b ........................................................... 16 re7/ad15/eccp2/p2a .............................................. 16 rf0/an5 ..................................................................... 17 rf1/an6/c2out ........................................................ 17 rf2/an7/c1out ........................................................ 17 rf3/an8 ..................................................................... 17 rf4/an9 ..................................................................... 17 rf5/an10/cv ref ....................................................... 17 rf6/an11 ................................................................... 17 rf7/ss ....................................................................... 17 rg0/eccp3/p3a........................................................ 18 rg1/tx2/ck2............................................................. 18 rg2/rx2/dt2............................................................. 18 rg3/ccp4/p3d.......................................................... 18 rg4/ccp5/p1d.......................................................... 18 rh0/a16 ..................................................................... 19 rh1/a17 ..................................................................... 19 rh2/a18 ..................................................................... 19 rh3/a19 ..................................................................... 19 rh4/an12/p3c........................................................... 19 rh5/an13/p3b........................................................... 19 rh6/an14/p1c........................................................... 19 rh7/an15/p1b........................................................... 19 rj0/ale ..................................................................... 20 rj1/oe ....................................................................... 20 rj2/wrl .................................................................... 20 rj3/wrh .................................................................... 20 rj4/ba0 ..................................................................... 20 rj5/ce ....................................................................... 20 rj6/lb ........................................................................ 20 rj7/ub ....................................................................... 20 v dd ............................................................................. 20 v ss ............................................................................. 20 pinout i/o descriptions ....................................................... 11 pir registers...................................................................... 92 pll lock time-out.............................................................. 30 pointer, fsr ....................................................................... 56 pop .................................................................................. 304 por. see power-on reset. porta associated registers ................................................ 105 functions .................................................................. 105 lata register .......................................................... 103 porta register ....................................................... 103 trisa register......................................................... 103 portb associated registers ................................................ 108 functions .................................................................. 108 latb register .......................................................... 106 portb register ....................................................... 106 rb3/int3:rb0/int0/flt0 pins, external................. 102 trisb register......................................................... 106 portc associated registers ................................................ 110 functions .................................................................. 110 latc register .......................................................... 109 portc register....................................................... 109 rc3/sck/scl pin .................................................... 187 trisc register......................................................... 109 portd ............................................................................. 128 associated registers ................................................ 113 functions .................................................................. 113 latd register .......................................................... 111 parallel slave port (psp) function........................... 111 portd register....................................................... 111 trisd register......................................................... 111
? 2005 microchip technology inc. ds39612b-page 387 PIC18F6525/6621/8525/8621 porte analog port pins ....................................................... 128 associated registers ................................................ 116 functions .................................................................. 116 late register........................................................... 114 porte register ....................................................... 114 psp mode select (pspmode bit) ................... 111, 128 re0/ad8/rd /p2d pin............................................... 128 re1/ad9/wr /p2c pin.............................................. 128 re2/ad10/cs /p2b pin ............................................. 128 trise register ......................................................... 114 portf associated registers ................................................ 119 functions .................................................................. 119 latf register........................................................... 117 portf register ....................................................... 117 trisf register ......................................................... 117 portg associated registers ................................................ 121 functions .................................................................. 121 latg register .......................................................... 120 portg register....................................................... 120 trisg register......................................................... 120 porth associated registers ................................................ 124 functions .................................................................. 124 lath register .......................................................... 122 porth register ....................................................... 122 trish register......................................................... 122 portj associated registers ................................................ 127 functions .................................................................. 127 latj register ........................................................... 125 portj register........................................................ 125 trisj register.......................................................... 125 postscaler, wdt assignment (psa bit) ............................................... 133 rate select (t0ps2:t0ps0 bits) .............................. 133 switching between timer0 and wdt ....................... 133 power-down mode. see sleep. power-on reset (por) ............................................... 30, 259 oscillator start-up timer (ost) .......................... 30, 259 power-up timer (pwrt) .................................... 30, 259 time-out sequence..................................................... 30 prescaler timer2....................................................................... 161 prescaler, capture ............................................................ 151 prescaler, timer0.............................................................. 133 assignment (psa bit) ............................................... 133 rate select (t0ps2:t0ps0 bits) .............................. 133 switching between timer0 and wdt ....................... 133 prescaler, timer2.............................................................. 154 pro mate ii universal device programmer ................... 319 product identification system ........................................... 393 program counter pcl, pclath and pclatu register ........................ 44 program memory extended microcontroller mode .................................. 39 instructions.................................................................. 45 two-word ........................................................... 46 interrupt vector ........................................................... 39 map and stack for pic18fx525 ................................. 40 map and stack for pic18fx621 ................................. 40 microcontroller mode .................................................. 39 microprocessor mode ................................................. 39 microprocessor with boot block mode........................ 39 reset vector ............................................................... 39 program verification ......................................................... 270 programming, device instructions.................................... 275 psp. see parallel slave port. pulse-width modulation. see pwm (ccp module) and pwm (eccp module). push................................................................................ 304 pwm (ccp module) ......................................................... 154 associated registers................................................ 156 ccpr4h:ccpr4l registers ................................... 154 duty cycle ................................................................ 154 example frequencies/resolutions ........................... 155 period ....................................................................... 154 setup for pwm operation ........................................ 155 tmr2 to pr2 match ......................................... 141, 154 tmr4 to pr4 match ................................................. 147 pwm (eccp module)....................................................... 160 associated registers................................................ 172 ccpr1h:ccpr1l registers ................................... 160 direction change in full-bridge output mode..................................................... 166 duty cycle ................................................................ 161 effects of a reset ..................................................... 171 enhanced pwm auto-shutdown .............................. 168 example frequencies/resolutions ........................... 161 full-bridge application example............................... 166 full-bridge mode ...................................................... 165 half-bridge mode...................................................... 163 half-bridge output mode applications example ....................................... 164 output configurations............................................... 162 output relationships (active-high) .......................... 162 output relationships (active-low) ........................... 163 period ....................................................................... 160 programmable dead-band delay............................. 168 setup for pwm operation ........................................ 171 start-up considerations............................................ 170 tmr2 to pr2 match ................................................. 160 q q clock ..................................................................... 154, 161 r ram. see data memory. rc oscillator....................................................................... 22 rcall .............................................................................. 305 rcon registers ............................................................... 101 register file........................................................................ 47 registers adcon0 (a/d control 0).......................................... 233 adcon1 (a/d control 1).......................................... 234 adcon2 (a/d control 2).......................................... 235 baudconx (baud rate control)............................. 216 ccpxcon (capture/compare/pwm control - ccp4, ccp5) .................................... 149 ccpxcon (capture/compare/pwm control - eccp1, eccp2, eccp3 modules).................. 157 cmcon (comparator control) ................................. 243 config1h (configuration 1 high)........................... 260 config2h (configuration 2 high)........................... 261 config2l (configuration 2 low) ............................ 261 config3h (configuration 3 high)........................... 262 config3l (configuration 3 low) ...................... 41, 262 config4l (configuration 4 low) ............................ 263 config5h (configuration 5 high)........................... 264 config5l (configuration 5 low) ............................ 263 config6h (configuration 6 high)........................... 265 config6l (configuration 6 low) ............................ 264
PIC18F6525/6621/8525/8621 ds39612b-page 388 ? 2005 microchip technology inc. config7h (configuration 7 high) ........................... 266 config7l (configuration 7 low)............................. 265 cvrcon (comparator voltage reference control)............................................ 249 device id register 2 ................................................. 266 devid1 (device id register 1)................................. 266 eccpxas (eccp auto-shutdown control) .............. 169 eccpxdel (pwm configuration)............................. 168 eecon1 (data eeprom control 1) .................... 63, 80 intcon (interrupt control) ......................................... 89 intcon2 (interrupt control 2).................................... 90 intcon3 (interrupt control 3).................................... 91 ipr1 (peripheral interrupt priority 1)........................... 98 ipr2 (peripheral interrupt priority 2)........................... 99 ipr3 (peripheral interrupt priority 3)......................... 100 lvdcon (low-voltage detect control).................... 255 memcon (memory control)....................................... 71 osccon (oscillator control) ..................................... 25 pie1 (peripheral interrupt enable 1) ........................... 95 pie2 (peripheral interrupt enable 2) ........................... 96 pie3 (peripheral interrupt enable 3) ........................... 97 pir1 (peripheral interrupt request (flag) 1) ................................................ 92 pir2 (peripheral interrupt request (flag) 2) ................................................ 93 pir3 (peripheral interrupt request (flag) 3) ................................................ 94 pspcon (parallel slave port control) ..................... 129 rcon (reset control) ........................................ 59, 101 rcstax (receive status and control) ..................... 215 sspcon1 (mssp control 1, i 2 c mode) .................. 184 sspcon1 (mssp control 1, spi mode) .................. 175 sspcon2 (mssp control 2, i 2 c mode) .................. 185 sspstat (mssp status, i 2 c mode)........................ 183 sspstat (mssp status, spi mode) ....................... 174 status ...................................................................... 58 stkptr (stack pointer) ............................................. 43 summary............................................................... 51?54 t0con (timer0 control)........................................... 131 t1con (timer 1 control).......................................... 135 t2con (timer 2 control).......................................... 141 t3con (timer3 control)........................................... 143 t4con (timer 4 control).......................................... 147 txstax (transmit status and control) .................... 214 wdtcon (watchdog timer control)........................ 267 reset .............................................................................. 305 reset........................................................................... 29, 259 mclr reset (normal operation) ................................. 29 mclr reset (sleep) ................................................... 29 power-on reset .......................................................... 29 programmable brown-out reset (bor) ..................... 29 reset instruction ...................................................... 29 stack full reset .......................................................... 29 stack underflow reset ............................................... 29 watchdog timer (wdt) reset.................................... 29 retfie ............................................................................. 306 retlw.............................................................................. 306 return ........................................................................... 307 return address stack ......................................................... 42 and associated registers ........................................... 43 revision history ................................................................ 377 rlcf................................................................................. 307 rlncf .............................................................................. 308 rrcf ................................................................................ 308 rrncf......................... ..................................................... 309 s sck .................................................................................. 173 sdi.................................................................................... 173 sdo .................................................................................. 173 serial clock, sck ............................................................. 173 serial data in (sdi)........................................................... 173 serial data out (sdo) ...................................................... 173 serial peripheral interface. see spi mode. setf................................................................................. 309 slave select (ss ).............................................................. 173 slave select synchronization ........................................... 179 sleep .............................................................................. 310 sleep......................................................................... 259, 269 software simulator (mplab sim) .................................... 318 software simulator (mplab sim30) ................................ 318 special event trigger. see compare (eccp mode). special event trigger. see compare (eccp module). special features of the cpu ............................................ 259 configuration registers .................................... 260?266 special function registers ................................................. 47 map............................................................................. 49 spi mode associated registers ................................................ 181 bus mode compatibility ............................................ 181 effects of a reset ..................................................... 181 master mode............................................................. 178 master/slave connection.......................................... 177 serial clock............................................................... 173 serial data in ............................................................ 173 serial data out ......................................................... 173 slave mode............................................................... 179 slave select.............................................................. 173 slave select synchronization ................................... 179 sleep operation........................................................ 181 spi clock .................................................................. 178 ss ..................................................................................... 173 sspov ............................................................................. 203 sspov status flag .......................................................... 203 sspstat register r/w bit ............................................................. 186, 187 status bits significance and initialization condition for rcon register ............................................. 31 subfwb .......................................................................... 310 sublw ............................................................................. 311 subwf............................................................................. 311 subwfb .......................................................................... 312 swapf ............................................................................. 312 t t0con register psa bit ..................................................................... 133 t0cs bit ................................................................... 133 t0ps2:t0ps0 bits.................................................... 133 t0se bit ................................................................... 133 table pointer operations (table)......................................... 64 tblrd .............................................................................. 313 tblwt.............................................................................. 314 time-out in various situations............................................ 31
? 2005 microchip technology inc. ds39612b-page 389 PIC18F6525/6621/8525/8621 timer0 ............................................................................... 131 16-bit mode timer reads and writes....................... 133 associated registers ................................................ 133 clock source edge select (t0se bit)....................... 133 clock source select (t0cs bit)................................ 133 operation .................................................................. 133 overflow interrupt ..................................................... 133 prescaler. see prescaler, timer0. timer1 ............................................................................... 135 16-bit read/write mode............................................ 137 associated registers ................................................ 139 operation .................................................................. 136 oscillator ........................................................... 135, 137 overflow interrupt ............................................. 135, 137 special event trigger (eccp) .......................... 137, 160 tmr1h register ....................................................... 135 tmr1l register........................................................ 135 use as a real-time clock ........................................ 138 timer2 ............................................................................... 141 associated registers ................................................ 142 mssp clock shift.............................................. 141, 142 operation .................................................................. 141 postscaler. see postscaler, timer2. pr2 register............................................. 141, 154, 160 prescaler. see prescaler, timer2. tmr2 register.......................................................... 141 tmr2 to pr2 match interrupt ........... 141, 142, 154, 160 timer3 ............................................................................... 143 associated registers ................................................ 145 operation .................................................................. 144 oscillator ........................................................... 143, 145 overflow interrupt ............................................. 143, 145 special event trigger (eccp) .................................. 145 tmr3h register ....................................................... 143 tmr3l register........................................................ 143 timer4 ............................................................................... 147 associated registers ................................................ 148 mssp clock shift...................................................... 148 operation .................................................................. 147 postscaler. see postscaler, timer4. pr4 register............................................................. 147 prescaler. see prescaler, timer4. tmr4 register.......................................................... 147 tmr4 to pr4 match interrupt ........................... 147, 148 timing diagrams a/d conversion......................................................... 355 acknowledge sequence ........................................... 206 asynchronous reception .......................................... 224 asynchronous transmission..................................... 222 asynchronous transmission (back to back) .................................................. 222 automatic baud rate calculation ............................. 220 auto-wake-up bit (wue) during normal operation ............................................. 225 auto-wake-up bit (wue) during sleep .................... 225 baud rate generator with clock arbitration ............. 200 brg reset due to sda arbitration during start condition ...................................... 209 brown-out reset (bor) ............................................ 341 bus collision during a repeated start condition (case 1) ............................................ 210 bus collision during a repeated start condition (case 2) ............................................ 210 bus collision during a start condition (scl = 0) .......................................... 209 bus collision during a stop condition (case 1)............................................ 211 bus collision during a stop condition (case 2)............................................ 211 bus collision during start condition (sda only) ....................................... 208 bus collision for transmit and acknowledge .................................................... 207 capture/compare/pwm (all eccp/ccp modules) ................................. 343 clko and i/o ........................................................... 338 clock synchronization .............................................. 193 clock/instruction cycle ............................................... 44 eusart synchronous receive (master/slave) .................................... 353 eusart synchronous transmission (master/slave)............................ 353 example spi master mode (cke = 0) ...................... 345 example spi master mode (cke = 1) ...................... 346 example spi slave mode (cke = 0) ........................ 347 example spi slave mode (cke = 1) ........................ 348 external clock (all modes except pll).................... 337 external memory bus timing for sleep (microprocessor mode)....................................... 77 external memory bus timing for tblrd (extended microcontroller mode) ....................... 76 external memory bus timing for tblrd (microprocessor mode)....................................... 76 full-bridge pwm output........................................... 165 half-bridge output.................................................... 163 i 2 c bus data............................................................. 349 i 2 c bus start/stop bits ............................................. 349 i 2 c master mode (7 or 10-bit transmission) ................................ 204 i 2 c master mode (7-bit reception) .......................... 205 i 2 c master mode first start bit timing ..................... 201 i 2 c slave mode (10-bit reception, sen = 0) ........... 190 i 2 c slave mode (10-bit reception, sen = 1) ........... 195 i 2 c slave mode (10-bit transmission) ..................... 191 i 2 c slave mode (7-bit reception, sen = 0) ............. 188 i 2 c slave mode (7-bit reception, sen = 1) ............. 194 i 2 c slave mode (7-bit transmission) ....................... 189 low-voltage detect .................................................. 256 master ssp i 2 c bus data ........................................ 351 master ssp i 2 c bus start/stop bits ......................... 351 parallel slave port (psp) ......................................... 344 parallel slave port (psp) read................................ 130 parallel slave port (psp) write ................................ 129 program memory read ............................................ 339 program memory write ............................................ 340 pwm auto-shutdown (prsen = 0, auto-restart disabled) ..................................... 170 pwm auto-shutdown (prsen = 1, auto-restart enabled) ...................................... 170 pwm direction change ............................................ 167 pwm direction change at near 100% duty cycle .............................................. 167 pwm output ............................................................. 154 repeated start condition ......................................... 202 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) ........................... 341 send break character sequence............................. 226 slave mode general call address sequence (7 or 10-bit address mode) .............................. 196
PIC18F6525/6621/8525/8621 ds39612b-page 390 ? 2005 microchip technology inc. slave synchronization .............................................. 179 slow rise time (mclr tied to v dd via 1 k ? resistor)................................................ 38 spi mode (master mode) .......................................... 178 spi mode (slave mode with cke = 0) ...................... 180 spi mode (slave mode with cke = 1) ...................... 180 stop condition receive or transmit mode ............... 206 synchronous reception (master mode, sren)....................................... 229 synchronous transmission....................................... 227 synchronous transmission (through txen) ........... 228 time-out sequence on por w/pll enabled (mclr tied to v dd via 1 k ? resistor) ............... 38 time-out sequence on power-up (mclr not tied to v dd ): case 1 .................................... 37 time-out sequence on power-up (mclr not tied to v dd ): case 2 .................................... 37 time-out sequence on power-up (mclr tied to v dd via 1 k ? resistor)............................ 37 timer0 and timer1 external clock ........................... 342 timing for transition between timer1 and osc1 (ec with pll active, scs1 = 1)............... 27 timing for transition between timer1 and osc1 (hs with pll active, scs1 = 1)............... 27 transition between timer1 and osc1 (hs, xt, lp)............................................. 26 transition between timer1 and osc1 (rc, ec)................................................... 28 transition from osc1 to timer1 oscillator ................. 26 wake-up from sleep via interrupt ............................. 270 timing specifications ........................................................ 337 a/d conversion requirements ................................. 355 capture/compare/pwm requirements .................... 343 clko and i/o requirements .................................... 338 eusart synchronous receive requirements.................................................... 353 eusart synchronous transmission requirements.................................................... 353 example spi mode requirements (master mode, cke = 0) ................................... 345 example spi mode requirements (master mode, cke = 1) ................................... 346 example spi mode requirements (slave mode, cke = 0) ..................................... 347 example spi slave mode requirements (cke = 1)................................... 348 external clock requirements ................................... 337 i 2 c bus data requirements (slave mode) ............... 350 i 2 c bus start/stop bits requirements (slave mode) .................................................... 349 master ssp i 2 c bus data requirements ................. 352 master ssp i 2 c bus start/stop bits requirements ................................................... 351 parallel slave port requirements............................. 344 pll clock ................................................................. 338 program memory read requirements ..................... 339 program memory write requirements ..................... 340 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................ 341 timer0 and timer1 external clock requirements ......................................... 342 trise register pspmode bit................................................... 111, 128 tstfsz ............................................................................ 315 two-word instructions example cases........................................................... 46 txstax register brgh bit .................................................................. 217 v voltage reference specifications..................................... 332 w wake-up from sleep ................................................. 259, 269 using interrupts ........................................................ 269 watchdog timer (wdt)............................................ 259, 267 associated registers ................................................ 268 control register........................................................ 267 postscaler................................................................. 268 programming considerations ................................... 267 rc oscillator............................................................. 267 time-out period ........................................................ 267 wcol ....................................................... 201, 202, 203, 206 wcol status flag.................................... 201, 202, 203, 206 www, on-line support .................... ................................... 5 x xorlw............................................................................. 315 xorwf ............................................................................ 316
? 2005 microchip technology inc. ds39612b-page 391 PIC18F6525/6621/8525/8621 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com in addition, there is a development systems information line which lists the latest versions of microchip?s development systems software products. this line also provides information on how customers can receive currently available upgrade kits. the development systems information line numbers are: 1-800-755-2345 ? united states and most of canada 1-480-792-7302 ? other international locations
PIC18F6525/6621/8525/8621 ds39612b-page 392 ? 2005 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39612b PIC18F6525/6621/8525/8621 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2005 microchip technology inc. ds39612b-page 393 PIC18F6525/6621/8525/8621 PIC18F6525/6621/8525/8621 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. part no. ? x /xx xxx pattern package temperature range device device PIC18F6525/6621/8525/8621 (1) , PIC18F6525/6621/8525/8621t (2) ; v dd range 4.2v to 5.5v pic18lf6x2x/8x2x (1) , pic18lf6x2x/8x2xt (2) ; v dd range 2.0v to 5.5v temperature range i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf6621-i/pt 301 = industrial temp., tqfp package, extended v dd limits, qtp pattern #301. b) pic18f8621-e/pt = extended temp., tqfp package, standard v dd limits. note 1: f = standard voltage range lf = extended voltage range 2: t = in tape and reel
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